# 2D Convolution with Line Buffer from HLS Tiny Tutorials

**URL:** <https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813>\
**Category:** Support\
**Created:** [July 6, 2021, 2:40pm UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813 "2021-07-06T14:40:39Z")\
**Posts on this page:** 6\
**Page:** 2

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 13, 2021, 7:25am UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/21 "2021-07-13T07:25:13Z")

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No, I do not have the script. But, you do not need one. Use the same image you are feeding from the notebook, perhaps you want to use a smaller image that can be fully captured by the ILA.

Mario

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**Author:** ![pedropinheiro2](https://avatars.discourse-cdn.com/v4/letter/p/2acd7d/32.png) [@pedropinheiro2](https://discuss.pynq.io/u/pedropinheiro2)\
**Post date:** [July 13, 2021, 8:36am UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/22 "2021-07-13T08:36:02Z")

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Hi @Wardo82,

Have you successfully used ILA?

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**Author:** ![Wardo82](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/wardo82/32/2131_2.png) [@Wardo82](https://discuss.pynq.io/u/Wardo82)\
**Post date:** [July 13, 2021, 2:17pm UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/23 "2021-07-13T14:17:56Z")

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Hi @pedropinheiro2, i have not used it yet. I’ll try this week.  
@marioruiz thanks for the reply, but **how** should i “use the same image”? In python is just sending an array as parameter, what about Vivado IP integrator and its debugging environment shown in the video?  
**From where**? VHDL testbench or such?  
I have never used ILA before.

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 13, 2021, 3:02pm UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/24 "2021-07-13T15:02:54Z")

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You do not need a test bench to use the ILA. The ILA also referred as ChipScope is hardware built in your design that allows you to capture the internal signal that are happening in your design.

> **[System Integrated Logic Analyzer (System ILA)](https://www.xilinx.com/products/intellectual-property/system-ila.html)**
>
> The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer which can be used to monitor the internal signals and interfaces of a design.

So, you download the overlay, configure the triggers in the ILA and run the notebook. Then you can observe what the ILA has captured.

Mario

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**Author:** ![pedropinheiro2](https://avatars.discourse-cdn.com/v4/letter/p/2acd7d/32.png) [@pedropinheiro2](https://discuss.pynq.io/u/pedropinheiro2)\
**Post date:** [July 14, 2021, 10:51am UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/25 "2021-07-14T10:51:13Z")

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Hi @marioruiz,

I believe I found the solution. The TKEEP and TSTRB sidebands from the output stream were always 0 and then the corresponding byte was always null and could safely be ignored.

From [https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Meaning-of-AXI-Stream-side-channel-signals/td-p/1118259](https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Meaning-of-AXI-Stream-side-channel-signals/td-p/1118259), I realized that the DMA needed those sidebands equal to 1 and I’ve changed my HLS code, introducing the following lines

```auto
axis pix_out_sidebands;
pix_out_sidebands.data = pix_out;
pix_out_sidebands.keep = 1;
pix_out_sidebands.strb = 1;
pix_out_sidebands.last = ((i==height-1) && (j==width-1)) ? 1 : 0;
dst << pix_out_sidebands;

```

Now, the DMA does not stall anymore.

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 14, 2021, 11:11am UTC](https://discuss.pynq.io/t/2d-convolution-with-line-buffer-from-hls-tiny-tutorials/2813/26 "2021-07-14T11:11:25Z")

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That’s fantastic. 😀

In your case tkeep is only one bit, more generally you will set up `keep = -1`, so all bits are 1.

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