# ADC to DMA stream not functioning

**URL:** <https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969>\
**Category:** Support\
**Created:** [August 29, 2021, 11:33pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969 "2021-08-29T23:33:27Z")\
**Posts on this page:** 5\
**Page:** 1

<div class="post-metadata">

**Author:** ![ldav](https://avatars.discourse-cdn.com/v4/letter/l/2bfe46/32.png) [@ldav](https://discuss.pynq.io/u/ldav)\
**Post date:** [August 29, 2021, 11:33pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969/1 "2021-08-29T23:33:27Z")

</div>

Hi,

I’m currently using PYNQ v2.6 on the RFSoC ZCU111 board (XCZU28DR-2FFVG1517E). I’ve attached an image of my block design and am using Vivado 2020.1 for my design environment.

I’m trying to load information from an ADC on the board into DMA, however I’m having no luck. My Jupyter notebook returns the following error. “DMA channel not started.”

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/f090dc1b25a672beef15b6fbede0712ba70fd769.png)

The first read returns an array of values, however every read after that returns 0s. After the ADC, I have a custom block generating a TLAST signal every 128 clock cycles, followed by an asynchronous FIFO to switch from 125 MHz (ADC clock) into 100 MHz (AXI-Lite).

Initially I thought the problem was no TLAST signal, however my custom design works in isolation. I believe the DMA may not be firing a TREADY signal after the first read, but this is just a guess and I’m also not sure how to fix that.

Has anyone had a similar issue? Any advice welcome 🙂

Block design - [dma\_write.pdf](https://discuss.pynq.io/uploads/short-url/wLJ61Q2BDGMbumOiQwqvXn6MaXH.pdf) (217.5 KB)

---

<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [September 1, 2021, 3:57pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969/2 "2021-09-01T15:57:49Z")

</div>

If you look at `dma.register_map` the `S2MM_SR` should give some indication as to why the DMA stopped. Can you copy the output here?

---

<div class="post-metadata">

**Author:** ![ldav](https://avatars.discourse-cdn.com/v4/letter/l/2bfe46/32.png) [@ldav](https://discuss.pynq.io/u/ldav)\
**Post date:** [September 28, 2021, 10:33pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969/3 "2021-09-28T22:33:28Z")

</div>

Hi, this is what dma.register\_map outputs.

RegisterMap {  
MM2S\_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic\_BD\_Enable=0, IOC\_IrqEn=0, Dly\_IrqEn=0, Err\_IrqEn=0, IRQThreshold=0, IRQDelay=0),  
MM2S\_DMASR = Register(Halted=0, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC\_Irq=0, Dly\_Irq=0, Err\_Irq=0, IRQThresholdSts=0, IRQDelaySts=0),  
MM2S\_CURDESC = Register(Current\_Descriptor\_Pointer=0),  
MM2S\_CURDESC\_MSB = Register(Current\_Descriptor\_Pointer=0),  
MM2S\_TAILDESC = Register(Tail\_Descriptor\_Pointer=0),  
MM2S\_TAILDESC\_MSB = Register(Tail\_Descriptor\_Pointer=0),  
MM2S\_SA = Register(Source\_Address=0),  
MM2S\_SA\_MSB = Register(Source\_Address=0),  
MM2S\_LENGTH = Register(Length=0),  
SG\_CTL = Register(SG\_CACHE=0, SG\_USER=0),  
S2MM\_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic\_BD\_Enable=0, IOC\_IrqEn=1, Dly\_IrqEn=0, Err\_IrqEn=0, IRQThreshold=1, IRQDelay=0),  
S2MM\_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=1, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC\_Irq=1, Dly\_Irq=0, Err\_Irq=1, IRQThresholdSts=0, IRQDelaySts=0),  
S2MM\_CURDESC = Register(Current\_Descriptor\_Pointer=0),  
S2MM\_CURDESC\_MSB = Register(Current\_Descriptor\_Pointer=0),  
S2MM\_TAILDESC = Register(Tail\_Descriptor\_Pointer=0),  
S2MM\_TAILDESC\_MSB = Register(Tail\_Descriptor\_Pointer=0),  
S2MM\_DA = Register(Destination\_Address=1938341888),  
S2MM\_DA\_MSB = Register(Destination\_Address=0),  
S2MM\_LENGTH = Register(Length=256)  
}

---

<div class="post-metadata">

**Author:** ![ldav](https://avatars.discourse-cdn.com/v4/letter/l/2bfe46/32.png) [@ldav](https://discuss.pynq.io/u/ldav)\
**Post date:** [September 28, 2021, 11:28pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969/4 "2021-09-28T23:28:16Z")

</div>

Update:

I managed to get the design working. It is an AXI4-Stream counter that is passed into AXI DMA and read via PYNQ. Essentially my previous design didn’t work because tlast wasn’t firing at the correct time, whilst tvalid was always high, causing bus contention.

Thanks for the assistance 🙂

---

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [March 18, 2022, 4:33pm UTC](https://discuss.pynq.io/t/adc-to-dma-stream-not-functioning/2969/5 "2022-03-18T16:33:17Z")

</div>

Hi @ldav , i’m trying to do the same project but i’m in stall with the ADC acquisition, could you share your BD and notebook for example?

Thanks  
Federico