# Array Transfer using Axis keeps waiting

**URL:** <https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439>\
**Category:** Support\
**Created:** [September 5, 2019, 5:02am UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439 "2019-09-05T05:02:27Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![Xingyu\_Zhou](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/xingyu_zhou/32/292_2.png) [@Xingyu\_Zhou](https://discuss.pynq.io/u/Xingyu_Zhou)\
**Post date:** [September 5, 2019, 5:02am UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/1 "2019-09-05T05:02:27Z")

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Hello. I am new to pynq. Trying to transfer arrays between PS and PL on Pynq-z1 board.

The program is a small neural network. I am imitating the writing from an online tutotial:  
[https://bitbucket.org/akhodamoradi/pynq\_interface/wiki/AXI\_DMA\_2](https://bitbucket.org/akhodamoradi/pynq_interface/wiki/AXI_DMA_2)

For my case, the function input is a (13,) shape float array. The output is a (2,) shape float array. Basically, it is a small neural network input and output.  
The neural network is generated from the tool called ‘hls4ml’ that converts a keras model into hls code.  
The generated code uses ap\_fixed as input and output and I am trying to send data as float arrays and then convert to ap\_fixed for generated code to run.  
So now I have passed simulation, generated ip and bit file. From the notebook file, seems that it stucks its asterisk at dma output receiving step:  
dma\_out.recvchannel.transfer(out\_buffer)  
dma\_out.recvchannel.wait()

Wondering if it has anything to do with the data type conversion or some other reason?  
I have attached the program files and block design.  
Thank you!

[fec\_latclass\_mlp2\_axispynq.zip](https://discuss.pynq.io/uploads/short-url/rWNQVE2wYQQyTjofZnfmqKLizis.zip) (415.8 KB)

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<div class="post-metadata">

**Author:** ![rock](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rock/32/32_2.png) [@rock](https://discuss.pynq.io/u/rock)\
**Post date:** [September 6, 2019, 1:16am UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/2 "2019-09-06T01:16:24Z")

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What about running the program in the following order:

```auto
def run_kernel():
    dma.sendchannel.transfer(in_buffer)
    dma.recvchannel.transfer(out_buffer)    
    resizer.write(0x00,0x81) # start
    dma.sendchannel.wait()
    dma.recvchannel.wait()

```

This is proved to be working for our examples here:  
[https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/Pynq-Z1/resizer/notebooks/resizer\_PL.ipynb](https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/Pynq-Z1/resizer/notebooks/resizer_PL.ipynb)

Also, I noticed that you instantiated the in and out buffers using np.float32. I am not sure about its impact because I have not done such a design in the past. Maybe safer to do integers?

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**Author:** ![radhen](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/radhen/32/627_2.png) [@radhen](https://discuss.pynq.io/u/radhen)\
**Post date:** [July 26, 2020, 1:21pm UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/3 "2020-07-26T13:21:59Z")

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Dear @rock, could you please explain what this mean and how to get those address?

> resizer.write(0x00,0x81) # start

I would like to use for my own IP to get the result from data processing, but it failed.

> ```
> dma.sendchannel.transfer(in_buffer)
> dma.recvchannel.transfer(out_buffer)    
> **custom_ip.write(in_buffer,out_buffer) # start**
> dma.sendchannel.wait()
> dma.recvchannel.wait()
> 
> ```

I made something like this. is that correct?  
thanks

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<div class="post-metadata">

**Author:** ![rock](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rock/32/32_2.png) [@rock](https://discuss.pynq.io/u/rock)\
**Post date:** [July 27, 2020, 5:31pm UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/4 "2020-07-27T17:31:49Z")

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That is usually needed when an IP requires a start signal. For your HLS IP, if you check the program comment generated by Vivado, you could find some register information about the generated IP. This is not required if you use your customized RTL IP.

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<div class="post-metadata">

**Author:** ![radhen](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/radhen/32/627_2.png) [@radhen](https://discuss.pynq.io/u/radhen)\
**Post date:** [August 25, 2020, 11:53am UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/5 "2020-08-25T11:53:48Z")

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> [@radhen](#):
>
> resizer.write(0x00,0x81) # start

Hi @rock Thank you for your answer, you are right.  
I am still curious about:

> [@](#):
>
> resizer.write(0x00,0x81) # start

As I checked the memory address:

> [@](#):
>
> //------------------------Address Info-------------------  
> // 0x00 : Control signals  
> // bit 0 - ap\_start (Read/Write/COH)  
> // bit 1 - ap\_done (Read/COR)  
> // bit 2 - ap\_idle (Read)  
> // bit 3 - ap\_ready (Read)  
> // bit 7 - auto\_restart (Read/Write)  
> // others - reserved  
> // 0x04 : Global Interrupt Enable Register  
> // bit 0 - Global Interrupt Enable (Read/Write)  
> // others - reserved  
> // 0x08 : IP Interrupt Enable Register (Read/Write)  
> // bit 0 - Channel 0 (ap\_done)  
> // bit 1 - Channel 1 (ap\_ready)  
> // others - reserved  
> // 0x0c : IP Interrupt Status Register (Read/TOW)  
> // bit 0 - Channel 0 (ap\_done)  
> // bit 1 - Channel 1 (ap\_ready)  
> // others - reserved  
> // 0x10 : Data signal of src\_rows  
> // bit 31~0 - src\_rows[31:0] (Read/Write)  
> // 0x14 : reserved  
> // 0x18 : Data signal of src\_cols  
> // bit 31~0 - src\_cols[31:0] (Read/Write)  
> // 0x1c : reserved  
> // 0x20 : Data signal of dst\_rows  
> // bit 31~0 - dst\_rows[31:0] (Read/Write)  
> // 0x24 : reserved  
> // 0x28 : Data signal of dst\_cols  
> // bit 31~0 - dst\_cols[31:0] (Read/Write)  
> // 0x2c : reserved  
> // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

but where is **0x81** from?

Thank you

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<div class="post-metadata">

**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [August 25, 2020, 12:08pm UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/6 "2020-08-25T12:08:21Z")

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0x81 = 10000001 in binary (bits 0 and 7 are set to 1. This will set ap\_start, and auto\_restart:

> [@radhen](#):
>
> // 0x00 : Control signals  
> // bit 0 - ap\_start (Read/Write/COH)  
> // bit 1 - ap\_done (Read/COR)  
> // bit 2 - ap\_idle (Read)  
> // bit 3 - ap\_ready (Read)  
> // bit 7 - auto\_restart (Read/Write)

Cathal

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<div class="post-metadata">

**Author:** ![radhen](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/radhen/32/627_2.png) [@radhen](https://discuss.pynq.io/u/radhen)\
**Post date:** [August 25, 2020, 6:59pm UTC](https://discuss.pynq.io/t/array-transfer-using-axis-keeps-waiting/439/7 "2020-08-25T18:59:50Z")

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Dear @cathalmccabe thank you very much, appreciate it. I totally understand now.