# Axi-s dma pl-\>ps

**URL:** <https://discuss.pynq.io/t/axi-s-dma-pl-ps/594>\
**Category:** Support\
**Created:** [October 22, 2019, 2:40pm UTC](https://discuss.pynq.io/t/axi-s-dma-pl-ps/594 "2019-10-22T14:40:45Z")\
**Posts on this page:** 1\
**Showing post:** 5

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**Author:** ![rashedkoutayni](https://avatars.discourse-cdn.com/v4/letter/r/58f4c7/32.png) [@rashedkoutayni](https://discuss.pynq.io/u/rashedkoutayni)\
**Post date:** [September 17, 2020, 3:41pm UTC](https://discuss.pynq.io/t/axi-s-dma-pl-ps/594/5 "2020-09-17T15:41:53Z")

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Hi @Kwstis,  
If you refer to my answer on another thread (link below), you can find a summary of my trials with DMA. The schematic in “6.pdf” shows how the different blocks should be connected with each others.  
Probably you need to click on the **“+”** sign near **Interrupt** port in the **AXI Interrupt Controller** block to get the single interrupt lines. Otherwise, you’re actually trying to connect the whole **interrupt bus** to the **IRQ\_F2P** port of the **ZYNQ**.

Was that helpful?

> [@AXI DMA not working on PYNQ-Z1](https://discuss.pynq.io/t/axi-dma-not-working-on-pynq-z1/715/8):
>
> As a summary, here are my trials: The corresponding designs can be found here: [1.pdf](https://discuss.pynq.io/uploads/short-url/fk3WIEWLcJSbjhv8m8w1loBMPil.pdf) (62.5 KB) [1\_modified.pdf](https://discuss.pynq.io/uploads/short-url/adZhVrxNufDIJHSHnAqzlToCBlI.pdf) (69.0 KB) [2.pdf](https://discuss.pynq.io/uploads/short-url/bknM3SbAge5mB2Whmvq6tiU0aNm.pdf) (70.4 KB) [3.pdf](https://discuss.pynq.io/uploads/short-url/fP69Q2yI69083ubIloTCxHC3DX6.pdf) (98.5 KB) [4.pdf](https://discuss.pynq.io/uploads/short-url/rhoTkmrYZdniMUpwPAsdox9PmgS.pdf) (78.5 KB) [5.pdf](https://discuss.pynq.io/uploads/short-url/rPeVgrASMPYMP5FUNHJeKuCF1Yz.pdf) (71.7 KB) [6.pdf](https://discuss.pynq.io/uploads/short-url/75dIOLs5lycZSe5tcsWpSEFf7ov.pdf) (77.1 KB) Here are my notes: 1- Don’t use Scatter/Gather. 2- If you want to use interrupt, use AXI Interrupt Controller. 3- if you’re making your custom IP in HLS, the input and output ports should be axis interfaces, while the return port should be s\_axilite: #pragma HLS INTERFACE axis…

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