# AXI stream with multi-DMA addition example never stops

**URL:** <https://discuss.pynq.io/t/axi-stream-with-multi-dma-addition-example-never-stops/2823>\
**Category:** Support\
**Created:** [July 9, 2021, 3:34pm UTC](https://discuss.pynq.io/t/axi-stream-with-multi-dma-addition-example-never-stops/2823 "2021-07-09T15:34:43Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![anoir\_nechi](https://avatars.discourse-cdn.com/v4/letter/a/bbe5ce/32.png) [@anoir\_nechi](https://discuss.pynq.io/u/anoir_nechi)\
**Post date:** [July 9, 2021, 3:34pm UTC](https://discuss.pynq.io/t/axi-stream-with-multi-dma-addition-example-never-stops/2823/1 "2021-07-09T15:34:43Z")

</div>

Hello I tried to replicate the same design as in this tutorial With a small change of using float instead of integers. This is my HLS code to generate the IP:  
streamADD.h file

```auto
#ifndef _STREAMADD_H_
#define _STREAMADD_H_

#include "ap_int.h"

struct axis_t
{
	float data;
	ap_int<1> last;
};

void sadd(axis_t *IN_1, axis_t *IN_2, unsigned int size, axis_t *OUT);

#endif

```

streamADD.cpp file

```auto
#include "streamADD.h"

void sadd(axis_t *IN_1, axis_t *IN_2, unsigned int size, axis_t *OUT)
{
#pragma HLS INTERFACE s_axilite port=size bundle=CTRL
#pragma HLS INTERFACE axis port=IN_1 depth=50
#pragma HLS INTERFACE axis port=IN_2 depth=50
#pragma HLS INTERFACE axis port=OUT depth=50

	for(int i = 0; i<size; i++)
	{
		axis_t	curr1 = *IN_1++;
		axis_t	curr2 = *IN_2++;

		curr1.data = curr1.data + curr2.data;

		*OUT++ = curr1;
	}
}

```

Then I followed the exact steps to generate the block design and got the attached block designs  
[design\_sadd.pdf](https://discuss.pynq.io/uploads/short-url/5R4JZry4KfOtRXqXGOptPmfhkZC.pdf) (94.4 KB)  
[stream\_add.pdf](https://discuss.pynq.io/uploads/short-url/b41Kgi9jqmGxDwFYwciEkcaETCs.pdf) (40.1 KB)  
and finally, I uploaded the bitstream and .hwh files to the pynq board Z1and I wrote the following code:

```auto
import time
from pynq import Overlay
import pynq.lib.dma
from pynq import Xlnk
import numpy as np
from pynq import MMIO
import random

ol = Overlay('/home/xilinx/jupyter_notebooks/add_tuto/sadd.bit') # check this path
ol.download() # this downloads your bitstream into FPGA
dma1 = ol.stream_add.sadd_dma1 # first DMA. Note that we had to access the hierarchy before accessing the DMA
dma2 = ol.stream_add.sadd_dma2 # second DMA
sadd_ip = MMIO(0x40000000, 0x10000) # we got this address from
xlnk = Xlnk()

length = 8

in_buffer1 = xlnk.cma_array(shape=(length,), dtype=np.float32) # input buffer 1
in_buffer2 = xlnk.cma_array(shape=(length,), dtype=np.float32) # input buffer 2
out_buffer = xlnk.cma_array(shape=(length,), dtype=np.float32) # output buffer

samples = random.sample(range(0, length), length)
np.copyto(in_buffer1, samples)
samples = random.sample(range(0, length), length)
np.copyto(in_buffer2, samples)

sadd_ip.write(0x10, length) # we got this address from Vivado source. Since we didn't do port=return, and we set a constant for ap_start, we only have to write length.
t_start = time.time()
print('sending ....')
dma1.sendchannel.transfer(in_buffer1)
dma2.sendchannel.transfer(in_buffer2)
dma1.recvchannel.transfer(out_buffer)
dma1.sendchannel.wait()
dma2.sendchannel.wait()
print('wait receive ....')
dma1.recvchannel.wait()
t_stop = time.time()
in_buffer1.close()
in_buffer2.close()
out_buffer.close()
print('Hardware execution time: ', t_stop-t_start)
for i in range(0, length):
    print('{}+{} = {}'.format(in_buffer1[i], in_buffer2[i], out_buffer[i]))

```

What did I do wrong? any Help?  
([Lab: Axistream Multiple DMAs (axis) — pp4fpgas 0.0.1 documentation](https://pp4fpgas.readthedocs.io/en/latest/axidma2.html))

---

<div class="post-metadata">

**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [July 13, 2021, 12:15pm UTC](https://discuss.pynq.io/t/axi-stream-with-multi-dma-addition-example-never-stops/2823/2 "2021-07-13T12:15:17Z")

</div>

Can you try read back the status register of the DMA? It may help point to the issue.

Cathal