# Board hangs when accessing AXI DMA from Python during RF loopback bring-up **URL:** \ **Category:** Support\ **Created:** [August 18, 2025, 4:26am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708 "2025-08-18T04:26:14Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![Ashritha\_S](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ashritha_s/32/7136_2.png) [@Ashritha\_S](https://discuss.pynq.io/u/Ashritha_S)\ **Post date:** [August 18, 2025, 4:26am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/1 "2025-08-18T04:26:14Z")
* * * ### Hello @marioruiz , ### Kindly help me in solving the below issue Title PYNQ 3.1 (ZU48DR / ZCU208): Board hangs when accessing AXI DMA from Python during RF loopback bring-up ### Environment - Board/SoC: **ZU48DR RFSoC** (ZCU208 class platform) - BSP/Image: **PYNQ 3.1** - Overlay: custom **base.bit + base.hwh** (contains RFDC + AXI DMA(s) + RX/TX chains) - Python: PYNQ notebooks (Jupyter) ### What I’m trying to do Validate an **RF loopback test** : DAC → (loopback) → ADC, with capture via **AXI DMA** to DDR and analysis in Python. ### Symptoms - As soon as I **access a DMA channel from Python** (e.g., create DMA object / call `sendchannel.transfer()` or `recvchannel.transfer()`), **the board hangs** : Jupyter becomes unresponsive, and I must **power-cycle/reboot**. - When I **simulate ADC data without DMA** , all plotting/processing works fine (so user-space flow is OK). - RFDC control via `xrfdc` works (I can program mixers etc.), but **DMA access causes the hang**. ### IP naming (from `ol.ip_dict.keys()` for context) Examples: `radio/receiver/channel_00/axi_dma_0`, `radio/receiver/channel_00/axi_dma_1`, `radio/transmitter/channel_30/axi_dma_2`, … (plus RFDC tiles/blocks, decimators, spectrum analyzers, etc.) ### Repro steps (high level) 1. `ol = Overlay('/run/media/base.bit')` (matching `base.hwh` present). 2. Create DMA handles and/or call transfers, e.g. 3. Requires board restart. Regards, Ashritha S ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 25, 2025, 1:39pm UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/2 "2025-08-25T13:39:31Z")
Hi @Ashritha_S, I moved your question to a new topic. How did you generate the PYNQ **3.1** image? Did you design your own overlay? Mario ---
**Author:** ![Ashritha\_S](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ashritha_s/32/7136_2.png) [@Ashritha\_S](https://discuss.pynq.io/u/Ashritha_S)\ **Post date:** [August 26, 2025, 3:44am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/3 "2025-08-26T03:44:47Z")
Hello @marioruiz Thanks for the reply. I am not using a pre-built image or overlay. Both the PYNQ image and the FPGA overlay/design are completely custom for my platform. My current challenge is related to DMA transfers in this custom setup. Please let me know if you need details on the overlay design or build process. Regards, Ashritha S ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 26, 2025, 10:58am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/4 "2025-08-26T10:58:36Z")
We found an issue with the memory allocator that it is now fixed in the 3.1.1 branch. I suggest you rebuild the image with this branch [GitHub - Xilinx/PYNQ at image\_v3.1.1](https://github.com/Xilinx/PYNQ/tree/image_v3.1.1) or apply this patch to your pynq deployment [fixing \<4KB buffer allocation issue (#1500) · Xilinx/PYNQ@2ad4c72 · GitHub](https://github.com/Xilinx/PYNQ/commit/2ad4c726cda3a0f8dd1a5e73b5ec0866892e7b39) ---
**Author:** ![Ashritha\_S](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ashritha_s/32/7136_2.png) [@Ashritha\_S](https://discuss.pynq.io/u/Ashritha_S)\ **Post date:** [August 26, 2025, 11:12am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/5 "2025-08-26T11:12:25Z")
Can u provide the python code to test RF Loopback test using DMA? ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 26, 2025, 5:13pm UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/6 "2025-08-26T17:13:12Z")
You will need to design your own overlay for this. You can find plenty of examples using the DMA ---
**Author:** ![Ashritha\_S](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ashritha_s/32/7136_2.png) [@Ashritha\_S](https://discuss.pynq.io/u/Ashritha_S)\ **Post date:** [August 28, 2025, 4:00am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/7 "2025-08-28T04:00:08Z")
Can u kindly share any one example of that overlay based on the DMA? ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 28, 2025, 7:23am UTC](https://discuss.pynq.io/t/board-hangs-when-accessing-axi-dma-from-python-during-rf-loopback-bring-up/8708/8 "2025-08-28T07:23:01Z")
You can see a DMA example here: > [@Tutorial: PYNQ DMA (Part 1: Hardware design)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133): > > PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …