# Build HLS IP in PYNQ-HelloWorld problem

**URL:** <https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481>\
**Category:** Support\
**Created:** [July 22, 2022, 1:11pm UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481 "2022-07-22T13:11:48Z")\
**Posts on this page:** 8\
**Page:** 1

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**Author:** ![Willy](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/willy/32/3440_2.png) [@Willy](https://discuss.pynq.io/u/Willy)\
**Post date:** [July 22, 2022, 1:11pm UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/1 "2022-07-22T13:11:48Z")

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Hi all,  
I’m testing the KV260 Kria and try to rebuild the PYNQ-HelloWorld for the KV260.

> **[GitHub - Xilinx/PYNQ-HelloWorld: This repository contains a "Hello World"...](https://github.com/Xilinx/PYNQ-HelloWorld)**
>
> This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework. - GitHub - Xilinx/PYNQ-HelloWorld: This repository contains a "Hello World" intro...

Because we need to use Vivado 2021 to build the Vivado project for the KV260.  
But I found a HLS IP building problem during make the resize source code.

> <https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/ip/src/xf_resize_accel_stream.cpp>

Error message:

> ERROR: [HLS 207-2971] no template named ‘ap\_axiu’ in namespace ‘xf::cv’; did you mean simply ‘ap\_axiu’? …  
> INFO: [HLS 207-4431] ‘ap\_axiu’ declared here: /tools/Xilinx/Vitis\_HLS/2021.1/common/technology/autopilot/ap\_axi\_sdata.h:141:1

If I change the version of Vivado to 2020.2, it can build pass without any error.  
I’m interesting why the following code will get different result with Vivado 2020.2 and 2022.1

> typedef xf::cv::ap\_axiu\<DATA\_WIDTH,1,1,1\> interface\_t;

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 22, 2022, 1:19pm UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/2 "2022-07-22T13:19:37Z")

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Hi @Willy,

We haven’t fully updated this repository yet. This will come with the next released of PYNQ.

However, you can try my branch [GitHub - mariodruiz/PYNQ-HelloWorld at 2022.1](https://github.com/mariodruiz/PYNQ-HelloWorld/tree/2022.1) which is the core of the updates to work with 2022.1.

Be aware that it is not fully tested.

Mario

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<div class="post-metadata">

**Author:** ![Willy](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/willy/32/3440_2.png) [@Willy](https://discuss.pynq.io/u/Willy)\
**Post date:** [July 25, 2022, 7:07am UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/4 "2022-07-25T07:07:39Z")

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Hi @marioruiz  
I install the vivado 2022.1 and get your test branch, but it seems still get the same error during building the resize ip.

```auto

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /media/willychiang/VM_Disk/tools/Xilinx/Vitis_HLS/2022.1/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/willychiang/VM_Disk/tools/Xilinx/Vitis_HLS/2022.1/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'willychiang' on host 'ubuntu3' (Linux_x86_64 version 5.15.0-41-generic) on Mon Jul 25 15:00:56 CST 2022
INFO: [HLS 200-10] On os Ubuntu 20.04.4 LTS
INFO: [HLS 200-10] In directory '/home/willychiang/Desktop/Test/PYNQ-HelloWorld/boards/ip'
...
INFO: [HLS 200-10] Analyzing design file 'src/xf_resize_accel_stream.cpp' ... 
ERROR: [HLS 207-2976] no template named 'ap_axiu' in namespace 'xf::cv'; did you mean simply 'ap_axiu'? (src/xf_resize_accel_stream.cpp:21:9)
INFO: [HLS 207-4436] 'ap_axiu' declared here (/media/willychiang/VM_Disk/tools/Xilinx/Vitis_HLS/2022.1/common/technology/autopilot/ap_axi_sdata.h:141:1)
WARNING: [HLS 207-5169] shift count is negative (/media/willychiang/VM_Disk/tools/Xilinx/Vitis_HLS/2022.1/common/technology/autopilot/ap_fixed_base.h:1036:13)
...
 
    while executing
"source build.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 5.44 seconds. Total CPU system time: 1.05 seconds. Total elapsed time: 5.13 seconds; peak allocated memory: 1.459 GB.
INFO: [Common 17-206] Exiting vitis_hls at Mon Jul 25 15:01:01 2022...

```

Modify the typedef for th ap\_axiu as below, then compiler can PASS…  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/354eb15c204cdbfad01a7c2d5cc5edee5b0db011.png)

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 25, 2022, 7:53am UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/5 "2022-07-25T07:53:48Z")

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Hi,

I forgot to commit that change. Thank you for pointing it out.  
Now, the change is in the repository.

Mario

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<div class="post-metadata">

**Author:** ![Willy](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/willy/32/3440_2.png) [@Willy](https://discuss.pynq.io/u/Willy)\
**Post date:** [July 25, 2022, 9:25am UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/6 "2022-07-25T09:25:51Z")

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Sorry to bother you again.  
I got the build error for the KV260 project.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/5/5eac911e30f52e653ca44066cf9c0ce605023c26.png)

Keying the “get\_board\_parts” in the TCL console, also get the same error message:

```auto
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /media/willychiang/VM_Disk/tools/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
xilinx.com:ac701:part0:1.4 xilinx.com:k26c:part0:1.2 xilinx.com:k26c:part0:1.3 xilinx.com:k26i:part0:1.2 xilinx.com:k26i:part0:1.3 xilinx.com:kc705:part0:1.6 xilinx.com:kcu105:part0:1.6 xilinx.com:kcu105:part0:1.7 xilinx.com:kcu116:part0:1.4 xilinx.com:kcu116:part0:1.5 xilinx.com:kcu1500:part0:1.2 xilinx.com:kv260_som:part0:1.2 xilinx.com:kv260_som:part0:1.3 xilinx.com:sp701:part0:1.0 xilinx.com:sp701:part0:1.1 xilinx.com:vc707:part0:1.4 xilinx.com:vc709:part0:1.8 xilinx.com:vck190:part0:2.2 xilinx.com:vck190:part0:3.0 xilinx.com:vck190_newl:part0:1.0 xilinx.com:vcu108:part0:1.6 xilinx.com:vcu108:part0:1.7 xilinx.com:vcu110:part0:1.4 xilinx.com:vcu118:part0:2.0 xilinx.com:vcu118:part0:2.3 xilinx.com:vcu118:part0:2.4 xilinx.com:vcu128:part0:1.0 xilinx.com:vcu129:part0:1.0 xilinx.com:vcu1525:part0:1.3 xilinx.com:vermeo_t1_mpsoc:part0:1.0 xilinx.com:vermeo_t1_rfsoc:part0:1.0 xilinx.com:vmk180:part0:2.2 xilinx.com:vmk180:part0:3.0 xilinx.com:vmk180_newl:part0:1.0 xilinx.com:zc702:part0:1.4 xilinx.com:zc706:part0:1.4 xilinx.com:zcu102:part0:3.3 xilinx.com:zcu102:part0:3.4 xilinx.com:zcu104:part0:1.1 xilinx.com:zcu106:part0:2.4 xilinx.com:zcu106:part0:2.5 xilinx.com:zcu106:part0:2.6 xilinx.com:zcu111:part0:1.2 xilinx.com:zcu111:part0:1.3 xilinx.com:zcu111:part0:1.4 xilinx.com:zcu1275:part0:1.0 xilinx.com:zcu1285:part0:1.0 xilinx.com:zcu208:part0:2.0 xilinx.com:zcu216:part0:2.0

```

Checked the installation information, the kv260 related options are checked correctly.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/6/66e846e240efde5013c764fea83b4da6d7fb60b9.png)

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 25, 2022, 9:53am UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/7 "2022-07-25T09:53:09Z")

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Hi,

Sorry for that, a few thing changed between versions.

Please pull the latest changes, and also make sure to run `make distclean` in the KV260/resize folder before rebuilding.

Mario

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<div class="post-metadata">

**Author:** ![Willy](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/willy/32/3440_2.png) [@Willy](https://discuss.pynq.io/u/Willy)\
**Post date:** [July 25, 2022, 11:01am UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/8 "2022-07-25T11:01:17Z")

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It is working now! Thanks again for your quickly support~

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [August 2, 2022, 7:37pm UTC](https://discuss.pynq.io/t/build-hls-ip-in-pynq-helloworld-problem/4481/9 "2022-08-02T19:37:58Z")

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