# Building PYNQ Base from source targeting ZCU104 board

**URL:** <https://discuss.pynq.io/t/building-pynq-base-from-source-targeting-zcu104-board/262>\
**Category:** Support\
**Created:** [June 30, 2019, 7:37pm UTC](https://discuss.pynq.io/t/building-pynq-base-from-source-targeting-zcu104-board/262 "2019-06-30T19:37:30Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![dcc3](https://avatars.discourse-cdn.com/v4/letter/d/bc8723/32.png) [@dcc3](https://discuss.pynq.io/u/dcc3)\
**Post date:** [June 30, 2019, 7:37pm UTC](https://discuss.pynq.io/t/building-pynq-base-from-source-targeting-zcu104-board/262/1 "2019-06-30T19:37:30Z")

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I have followed the instructions on how to build the PYNQ project from source on a learn page ( [Tutorial: Rebuilding the PYNQ base overlay](https://discuss.pynq.io/t/tutorial-rebuilding-the-pynq-base-overlay/61)) but I get an error during the “vivado -mode batch -source build\_bitstream.tcl -notrace”:

write\_bitstream failed  
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:  
base\_i/video/hdmi\_out/frontend/inst/v\_hdmi\_tx/inst ()  
base\_i/video/hdmi\_in/frontend/inst/v\_hdmi\_rx/inst ()  
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

I am using the 2.4 version of PYNQ with Vivado 2018.3. This method works perfectly when I build from source for my Z1 board just not the ZCU104 board. Would anyone have some advice on how to overcome this issue?

Thanks!

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [June 30, 2019, 8:05pm UTC](https://discuss.pynq.io/t/building-pynq-base-from-source-targeting-zcu104-board/262/2 "2019-06-30T20:05:37Z")

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You need a license for some of the IP used in this design.

If you are from a university, you can request a donation of this IP from the Xilinx University Program.

> **[University](https://www.xilinx.com/support/university.html)**

If you just want to try it, you should also be able to use the evaluation licenses:

> **[HDMI](https://www.xilinx.com/products/intellectual-property/hdmi.html)**
>
> The LogiCORE™ IP HDMI Reference Design implements HDMI digital video interface in Xilinx FPGAs.

Cathal

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**Author:** ![dcc3](https://avatars.discourse-cdn.com/v4/letter/d/bc8723/32.png) [@dcc3](https://discuss.pynq.io/u/dcc3)\
**Post date:** [July 2, 2019, 2:20am UTC](https://discuss.pynq.io/t/building-pynq-base-from-source-targeting-zcu104-board/262/3 "2019-07-02T02:20:28Z")

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Thanks for the suggestion. I have applied for access to the XUP.