# CacheMetadataError ZCU102 PYNQ3.0.1 Vivado2022.1

**URL:** <https://discuss.pynq.io/t/cachemetadataerror-zcu102-pynq3-0-1-vivado2022-1/8093>\
**Category:** Support\
**Created:** [February 28, 2025, 3:28am UTC](https://discuss.pynq.io/t/cachemetadataerror-zcu102-pynq3-0-1-vivado2022-1/8093 "2025-02-28T03:28:02Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![buloruabutata](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/buloruabutata/32/5768_2.png) [@buloruabutata](https://discuss.pynq.io/u/buloruabutata)\
**Post date:** [February 28, 2025, 3:28am UTC](https://discuss.pynq.io/t/cachemetadataerror-zcu102-pynq3-0-1-vivado2022-1/8093/1 "2025-02-28T03:28:02Z")

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[design\_1.hwh](https://discuss.pynq.io/uploads/short-url/aNPGnlaqLKNZ4BE4vPrbg0ovwnf.hwh) (308.4 KB)  
[design\_1.tcl](https://discuss.pynq.io/uploads/short-url/utF8rG3986gznmxgveUF3BrcJFd.tcl) (53.8 KB)  
how to sollve this problem？Error message below:

```auto
CacheMetadataError  
...
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:452, in HwhFrontend._resolve_subordinate_addressing(self)
    450 for i in self._root.iter("MEMRANGE"):
    451 if i.get("MEMTYPE") == "REGISTER" or i.get("MEMTYPE") == "MEMORY":
--> 452 core = self.blocks[i.get("INSTANCE")]
    453 port = core.ports[i.get("SLAVEBUSINTERFACE")]
    454 if isinstance(port, SubordinatePort):

KeyError: 'axil_m'

```

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<div class="post-metadata">

**Author:** ![buloruabutata](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/buloruabutata/32/5768_2.png) [@buloruabutata](https://discuss.pynq.io/u/buloruabutata)\
**Post date:** [February 28, 2025, 3:29am UTC](https://discuss.pynq.io/t/cachemetadataerror-zcu102-pynq3-0-1-vivado2022-1/8093/2 "2025-02-28T03:29:08Z")

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I am trying to read data from PS with Datamover. I encountered this problem when loading the bit stream.

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<div class="post-metadata">

**Author:** ![buloruabutata](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/buloruabutata/32/5768_2.png) [@buloruabutata](https://discuss.pynq.io/u/buloruabutata)\
**Post date:** [February 28, 2025, 3:47am UTC](https://discuss.pynq.io/t/cachemetadataerror-zcu102-pynq3-0-1-vivado2022-1/8093/3 "2025-02-28T03:47:15Z")

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> [@buloruabutata](#):
>
> `HwhFrontend._resolve_subordinate_addressing`

In this link ([https://discussion.PYNQ.io/t/impossible-to-add-an-axi4lite-output-port-in-the-block-design-pynq/7965/3](https://discussion.PYNQ.io/t/impossible-to-add-an-axi4lite-output-port-in-the-block-design-pynq/7965/3)), block design does not support AXI or AXIL as the external interface of module design, so I’m going to give it a try.