# Can't download bitstream **URL:** \ **Category:** Support\ **Created:** [February 15, 2022, 8:17pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690 "2022-02-15T20:17:56Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![ggillett](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ggillett/32/953_2.png) [@ggillett](https://discuss.pynq.io/u/ggillett)\ **Post date:** [February 15, 2022, 8:17pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/1 "2022-02-15T20:17:56Z")
Hi, We have created a custom image for a Zynq 7000 series board using the sdbuild procedure. The image boots and things work as expected until we attempt to instantiate an Overlay. ```python --------------------------------------------------------------------------- TimeoutError Traceback (most recent call last) TimeoutError: [Errno 110] Connection timed out During handling of the above exception, another exception occurred: TimeoutError Traceback (most recent call last) in ----> 1 o=Overlay('uart_loopback.bit') /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py in __init__ (self, bitfile_name, dtbo, download, ignore_version, device) 352 353 if download: --> 354 self.download() 355 356 self. __doc__ = _build_docstring(self._ip_map._description, /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py in download(self, dtbo) 418 Clocks.set_pl_clk(i) 419 --> 420 super().download(self.parser) 421 if dtbo: 422 super().insert_dtbo(dtbo) /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/bitstream.py in download(self, parser) 185 186 """ --> 187 self.device.download(self, parser) 188 189 def remove_dtbo(self): /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/pl_server/embedded_device.py in download(self, bitstream, parser) 594 fd.write(str(flag)) 595 with open(self.BS_FPGA_MAN, 'w') as fd: --> 596 fd.write(bitstream.binfile_name) 597 598 self.set_axi_port_width(parser) TimeoutError: [Errno 110] Connection timed out ``` ```auto xilinx@pynq:~$ xbutil list INFO: Found total 1 card(s), 1 are usable ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ System Configuration OS name: Linux Release: 5.4.0-xilinx-v2020.2 Version: #1 SMP PREEMPT Fri Feb 11 16:30:23 UTC 2022 Machine: armv7l Glibc: 2.31 Distribution: PynqLinux, based on Ubuntu 20.04 Now: Tue Feb 15 20:14:24 2022 GMT ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ XRT Information Version: 2.8.0 Git Hash: 7c93966ead2dec777b92bdc379893f22b5bd561e Git Branch: temp Build Date: 2022-02-11 16:44:44 ZOCL: 2.8.0,7c93966ead2dec777b92bdc379893f22b5bd561e Failed to open device[0] ERROR: Card index 0 is out of range ``` Any thoughts on how to debug? Cheers, Geoff. ---
**Author:** ![ggillett](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ggillett/32/953_2.png) [@ggillett](https://discuss.pynq.io/u/ggillett)\ **Post date:** [February 16, 2022, 1:28pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/2 "2022-02-16T13:28:17Z")
More info ```auto [24945.485601] fpga_manager fpga0: writing uart_loopback.bin to Xilinx Zynq FPGA Manager [24947.992420] fpga_manager fpga0: Timeout waiting for PCFG_INIT [24947.996878] fpga_manager fpga0: Error preparing FPGA for writing fpga-full { compatible = "fpga-region"; fpga-mgr = <0x03>; ranges; #address-cells = <0x01>; #size-cells = <0x01>; phandle = <0x13>; }; devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; clocks = <0x01 0x0c 0x01 0x0f 0x01 0x10 0x01 0x11 0x01 0x12>; clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; interrupt-parent = <0x04>; interrupts = <0x00 0x08 0x04>; phandle = <0x03>; reg = <0xf8007000 0x100>; syscon = <0x08>; }; ``` Any insights appreciated. ---
**Author:** ![ggillett](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ggillett/32/953_2.png) [@ggillett](https://discuss.pynq.io/u/ggillett)\ **Post date:** [February 18, 2022, 6:31pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/3 "2022-02-18T18:31:20Z")
```auto from pynq import Overlay o=Overlay('design_1.bit') ``` Directly after booting, fails with a timeout. DMESG shows ```auto [736.723243] fpga_manager fpga0: writing design_1.bin to Xilinx Zynq FPGA Manager [739.455939] fpga_manager fpga0: Error after writing image data to FPGA [739.461832] fpga_manager fpga0: writing design_1.bin to Xilinx Zynq FPGA Manager [741.969149] fpga_manager fpga0: Timeout waiting for PCFG_INIT [741.973608] fpga_manager fpga0: Error preparing FPGA for writing ``` The bitstream and corresponding HWH are generated in Vivado 2020.2 from a n upgraded 2020.1 project which loads on our 2.5 based image build using the Petalinux flow. Is the missing IRQ expected during boot? Perhaps the interrupt is not needed when FPGA manager is used? ```auto [10.277828] zocl: loading out-of-tree module taints kernel. [10.287758] [drm] Probing for xlnx,zocl **[10.287792] zocl-drm amba:zyxclmm_drm: IRQ index 0 not found** [10.292274] [drm] PR Isolation addr 0x0 [10.334772] [drm] Initialized zocl 2018.2.1 20180313 for amba:zyxclmm_drm on minor 0 [11.854714] random: crng init done [11.854728] random: 7 urandom warning(s) missed due to ratelimiting [16.245128] macb e000b000.ethernet eth0: link up (100/Full) [16.245179] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [20.125404] [drm] Pid 410 opened device [20.125495] [drm] Pid 410 closed device [20.126268] [drm] Pid 410 opened device [20.138953] [drm] Pid 410 closed device [24.995003] [drm] Pid 265 opened device [24.995063] [drm] Pid 265 closed device [24.995709] [drm] Pid 265 opened device [25.001867] [drm] Pid 265 opened device [25.001951] [drm] Pid 265 closed device [25.002671] [drm] Pid 265 opened device [25.002724] [drm] Pid 265 closed device [25.002881] [drm] Pid 265 opened device ``` Again any advice or insights on how to debug would be appreciated. How do I get more information on `fpga_manager fpga0: Error after writing image data to FPGA`? ---
**Author:** ![stf](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/stf/32/2724_2.png) [@stf](https://discuss.pynq.io/u/stf)\ **Post date:** [February 22, 2022, 2:19pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/4 "2022-02-22T14:19:26Z")
Hi Geoff, Would it be possible for you to try configuring the bitstream via JTAG to see if that is able to program the PL correctly? Just checking also, you are not attempted to load an encrypted bitstream? All the best, Shane ---
**Author:** ![ggillett](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ggillett/32/953_2.png) [@ggillett](https://discuss.pynq.io/u/ggillett)\ **Post date:** [February 22, 2022, 4:17pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/5 "2022-02-22T16:17:21Z")
Haha well that is embarrassing, no it did not program over jtag because the bitstream was targeting the wrong part, Doh! Thanks for the help Shane, the overlay loads now. I should get some time to look at a the BDC issue over the next few days. Cheers, Geoff. ---
**Author:** ![stf](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/stf/32/2724_2.png) [@stf](https://discuss.pynq.io/u/stf)\ **Post date:** [February 22, 2022, 4:30pm UTC](https://discuss.pynq.io/t/cant-download-bitstream/3690/6 "2022-02-22T16:30:41Z")
No worries Geoff, it’s easily done :). It would be helpful if the tools printed out a nicer error message when there is an attempt to load an incorrect bitstream. All the best, Shane