# Can't find the axi IP we creat from HLS&vivado tools

**URL:** <https://discuss.pynq.io/t/cant-find-the-axi-ip-we-creat-from-hls-vivado-tools/2243>\
**Category:** Support\
**Created:** [January 14, 2021, 2:14am UTC](https://discuss.pynq.io/t/cant-find-the-axi-ip-we-creat-from-hls-vivado-tools/2243 "2021-01-14T02:14:59Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![AllenChenChao](https://avatars.discourse-cdn.com/v4/letter/a/7bcc69/32.png) [@AllenChenChao](https://discuss.pynq.io/u/AllenChenChao)\
**Post date:** [January 14, 2021, 2:14am UTC](https://discuss.pynq.io/t/cant-find-the-axi-ip-we-creat-from-hls-vivado-tools/2243/1 "2021-01-14T02:14:59Z")

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[can’t find the exampe IP on pynq](https://forums.xilinx.com/t5/Vivado/HLS%E7%9A%84axi%E6%8E%A5%E5%8F%A3%E7%9A%84IP%E6%97%A0%E6%B3%95%E5%9C%A8vivado%E4%B8%AD%E4%BD%BF%E7%94%A8/m-p/1194467#M7381)

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [January 14, 2021, 7:31am UTC](https://discuss.pynq.io/t/cant-find-the-axi-ip-we-creat-from-hls-vivado-tools/2243/2 "2021-01-14T07:31:57Z")

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It looks like your IP doesn’t have an AXI Slave interface and therefore it won’t be in the Zynq PS memory map and PYNQ won’t auto discover it.  
You have an AXI Master on your IP connected to the HP port, so your IP maps the PS DRAM into _its_ memory space.  
It looks like the ap\_control interface should be an AXI slave interface.

CHeck the documentation for the **INTERFACE** pragma in HLS.

You may want to add this, but you should check the documentation and make sure you understand what this is doing before you add it:

#pragma HLS INTERFACE s\_axilite port = return

This may be helpful:  
[https://xilinx.github.io/Vitis-Tutorials/2020-1/docs/my-first-program/cpp\_kernel.html](https://xilinx.github.io/Vitis-Tutorials/2020-1/docs/my-first-program/cpp_kernel.html)

Cathal