# Changing the IP in the Composable Pipeline

**URL:** <https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301>\
**Category:** Learn\
**Created:** [June 3, 2022, 5:50pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301 "2022-06-03T17:50:14Z")\
**Posts on this page:** 20\
**Page:** 1

<div class="post-metadata">

**Author:** ![jcollier](https://avatars.discourse-cdn.com/v4/letter/j/9dc877/32.png) [@jcollier](https://discuss.pynq.io/u/jcollier)\
**Post date:** [June 3, 2022, 5:50pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/1 "2022-06-03T17:50:15Z")

</div>

These steps are to use new vitis vision-based functions or custom HLS and insert them into the Composable Pipeline. I hope this helps to unravel how to extend this great tool. Please let me know if you have feedback.

**High level overview:**

- Create new IP
- Add the new IP to the Composable Pipeline Vivado design
- Build the new bitstream
- Edit the Composable Pipeline Python code to support the new function

For this example, I will create a gammacorrection HLS block and insert it into the pipeline.

#### Creating a new IP block using OpenCV

The existing Composable Pipeline functions are in PYNQ\_Composable\_Pipeline/src. NOTE: the name of the directory and the cpp file are expected by the Makefile to be the name of the xfOpenCV kernel function. In this case, it would be gammacorrection.

```auto
cd PYNQ_Composable_Pipeline/src
mkdir gammacorrection
cp LUT/LUT.cpp gammacorrection/gammacorrection.cpp

```

Make the necessary edits:

- include the correct vitis vision hpp file
- change the function name to be the name of the xfOpenCV kernel + \_accel
- Make sure that the #defines are correct ( remove unused ones and create any new ones )
- Edit the offsets as necessary. The general pipeline framework expects rows at 0x10 and cols at 0x18. Look in the HWH file to get the offsets if needed

In this example, the gammacorrection.cpp file is:

```auto
// Copyright (C) 2021 Xilinx, Inc
//
// SPDX-License-Identifier: BSD-3-Clause

#include "hls_stream.h"
#include "common/xf_common.hpp"
#include "common/xf_infra.hpp"
#include "imgproc/xf_gammacorrection.hpp"

#define DATA_WIDTH 24
#define NPIX XF_NPPC1

/* set the height and width */
#define WIDTH 1920
#define HEIGHT 1080
#define TYPE XF_8UC3

typedef xf::cv::ap_axiu<DATA_WIDTH,1,1,1> interface_t;
typedef hls::stream<interface_t> stream_t;

// https://xilinx.github.io/Vitis_Libraries/vision/2020.2/api-reference.html#custom-convolution
void gammacorrection_accel(stream_t& stream_in,
                    stream_t& stream_out,
                    unsigned int rows,
                    unsigned int cols,
                    float gaPreparing to unpack .../gir1.2-gtksource-3.0_3.24.11-2_amd64.deb ...
egister both port=stream_in
#pragma HLS INTERFACE axis register both port=stream_out
#pragma HLS INTERFACE s_axilite port=rows offset=0x10
#pragma HLS INTERFACE s_axilite port=cols offset=0x18
#pragma HLS INTERFACE s_axilite port=gammaval offset=0x20
#pragma HLS INTERFACE s_axilite port=return

    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> img_in(rows, cols);
    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> img_out(rows, cols);

#pragma HLS DATAFLOW

    // Convert stream in to xf::cv::Mat
    xf::cv::AXIvideo2xfMat<DATA_WIDTH, TYPE, HEIGHT, WIDTH, NPIX>(stream_in, img_in);

    // Run xfOpenCV kernel:
    xf::cv::gammacorrection<TYPE,TYPE,HEIGHT,WIDTH,NPIX>(img_in, img_out, gammaval);

    // Convert xf::cv::Mat to stream
    xf::cv::xfMat2AXIvideo<DATA_WIDTH, TYPE, HEIGHT, WIDTH, NPIX>(img_out, stream_out);
}

```

#### Build the vitis IP

The Makefile builds the HLS in boards/ip/vitis\_vision. If the compile is not successful, delete the boards/ip/vitis\_vision/.vhlsprj directory and rebuild.

```auto
cd ../boards/ZCU104.build
make vision_ip

```

Now the IP is available to vivado as the composable pipeline project already has this directory in the IP sources.

#### Modify the Vivado project

Open the project in boards/ZCU104.build/cv\_dfx\_4\_pr/cv\_dfx\_4\_pr.xpr

Navigate to Open Block design Double-click on Composable Choose one of the IP blocks to remove - like rgb2hsv - and remove it.  
Add in the New Ip by clicking the ‘+’ icon and searching for gammacorrection Move it into the location of the old IP connect the pins (there is only one way to do this ) Click on the gammacorrection IP and rename it by removing the \_0 at the end Navigate to Window-\>Address Editor and go to the bottom for “Unassigned entry” and click assign

Now, build it

- Run Synthesis
- Run Implementation
- Run Generate Bitstream

#### Collect the overlay files and package everything

After editing the design, the overlay files will be out of date. Download the overlay.tcl file (culled from the main tcl file)

```auto
# collect the overlay files 
vivado -mode batch -source overlay.tcl -notrace

# Make the dictionary
make dict

# Make the ZIP file for transferring to the board 
make zip 

# copy the file to the board:
scp composable-video-pipeline-zcu104-v1_0_2.zip xilinx@<board>:/tmp

```

#### Install the new overlays

Log into the board as the xilinx user

```auto
sudo -i 
cd ~xilinx/jupyter_notebooks
# Install the overlay directory and file 
unzip /tmp/composable-video-pipeline-zcu104-v1_0_2.zip 

```

Note: In the Jupyter Notebooks, reference the overlay path by full path ol = Overlay(“/home/xilinx/jupyter\_notebooks/overlay/cv\_dfx\_4\_pr.bit”)

#### Edit the Composable Pipeline python

On the board, the pynq\_composable files are located at /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq\_composable/

Edit the libs.py to get base functionality. apps.py needs to be edited for the interactive widgets to work (future work)

There are 2 main steps. The first is to install the new accelerator in the VitisVisionIP class to get some common functionaly. The second is to add the new class that calls the functionality.

Step 1:  
Edit the bindto array in the VitisVisionIP class to replace the removed accelerator with the new one. In this case, it looks like:

```auto
bindto = [
        'xilinx.com:hls:dma2video_accel:1.0',
        'xilinx.com:hls:video2dma_accel:1.0',
        'xilinx.com:hls:rgb2gray_accel:1.0',
        'xilinx.com:hls:gaussian_filter_accel:1.0',
        'xilinx.com:hls:gray2rgb_accel:1.0',
        'xilinx.com:hls:pyrUp_accel:1.0',
        'xilinx.com:hls:subtract_accel:1.0',
        'xilinx.com:hls:gammacorrection_accel:1.0',
        'xilinx.com:hls:rgb2xyz_accel:1.0',
        "xilinx.com:hls:absdiff_accel:1.0",
        "xilinx.com:hls:add_accel:1.0",
        "xilinx.com:hls:bitwise_and_accel:1.0",
        "xilinx.com:hls:bitwise_not_accel:1.0",
        "xilinx.com:hls:bitwise_or_accel:1.0",
        "xilinx.com:hls:bitwise_xor_accel:1.0",
    ]

```

Step 2: Add the new functionality. This is where the mapping of python variables and registry maps occurs. The rows and cols happens because it inherits from the VitisVisionIP. Other axilite variables get mapped here. In this case, gammaval needs to be added. Changing the variable in Python doesn’t cause it to be written to the register map by default. So a getter/setter is created to actually write the value. In this case, it writes the float to 0x20.

Note: Examining cv\_dfx\_4\_pr.hwh will show the register maps. In this case, under gammacorrection\_accel: rows: ADDRESS\_OFFSET=16 → 0x10 cols: ADDRESS\_OFFSET=24 → 0x18 gammaval: ADDRESS\_OFFSET=32 → -x20

```auto
class gammacorrection(VitisVisionIP):
    """gammacorrection"""

    bindto = ['xilinx.com:hls:gammacorrection_accel:1.0']

    def __init__ (self, description):
        print("gammacorrection: init")
        super(). __init__ (description=description)
        self._gammaval = 1.0

    def start(self):
        super().start()
        self.gammaval=1.0
        print("gammacorrection: start")

    @property
    def gammaval(self) -> float:
        return self._gammaval

    @gammaval.setter
    def gammaval(self, gammaval: float):
        if not isinstance(gammaval, (float, int)):
            raise ValueError("gammaval must a number")

        self._gammaval = float(gammaval)
        self.write(0x20, _float2int(self.gammaval))
        #print("setting gammaval to " + str(self.gammaval))

```

#### Test it in the Jupyter Notebook

Open the pynq\_composable/custom\_pipeline/02\_first\_custom\_pipeline.ipynb notebook. File → Make a Copy and save it as GammaCorrection

Changes:

```auto
#Downlaod Composable Overlay: 
ol = Overlay("/home/xilinx/jupyter_notebooks/overlay/cv_dfx_4_pr.bit")

#Let us Compose:
gamma = cpipe.gammacorrection_accel

video_pipeline = [cpipe.hdmi_source_in, gamma, cpipe.hdmi_source_out]

cpipe.compose(video_pipeline)

#Play with IP
import time
for i in range(0,1000):
    gamma.gammaval = i*0.0025
    time.sleep(0.01)
gamma.gammaval=1

```

Then run the Jupyter Notebook.

#### TODO:

- insert new functions into the DFX region
- Path for the overlays isn’t default
- Make the apps work

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 3, 2022, 6:44pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/2 "2022-06-03T18:44:59Z")

</div>

Hi @jcollier,

Thank you for sharing this 😀

One small comment, the bindto of the `VitisVisionIP` shouldn’t include the vlnv of the derived objects. So, `'xilinx.com:hls:gammacorrection_accel:1.0'`, should only be part of the `gammacorrection` class.  
Otherwise, there’s a risk of `VitisVisionIP` being assigned as driver to the gammacorrection IP.

Mario

---

<div class="post-metadata">

**Author:** ![jcollier](https://avatars.discourse-cdn.com/v4/letter/j/9dc877/32.png) [@jcollier](https://discuss.pynq.io/u/jcollier)\
**Post date:** [June 3, 2022, 6:49pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/3 "2022-06-03T18:49:52Z")

</div>

Thanks much. I will update my instructions. I was unclear how and why I would do that, but it worked.

---

<div class="post-metadata">

**Author:** ![WhatTechTalk\_Calvin](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/whattechtalk_calvin/32/3987_2.png) [@WhatTechTalk\_Calvin](https://discuss.pynq.io/u/WhatTechTalk_Calvin)\
**Post date:** [November 4, 2022, 2:07pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/4 "2022-11-04T14:07:15Z")

</div>

hello, I have a problem,

# collect the overlay files

vivado -mode batch -source overlay.tcl -notrace  
Can you share the “overlay.tcl”? I don’t kown how to code the file.

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 1:53pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/5 "2023-04-03T13:53:50Z")

</div>

Hi @jcollier,

A great step by step guide, Did you ever attempt the same procedure but to insert new functions into the dfx region?  
@marioruiz have you seen any posts on this subject? I can’t find any myself.

I feel like this would be a lot more beneficial for adding new filters to the pipeline as am I right in saying it would require only the generation of a partial bitstream and not the whole project again?

Regards,  
Cameron

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 3, 2023, 2:28pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/6 "2023-04-03T14:28:22Z")

</div>

Hi @cking,

Adding new reconfigurable modules to reconfigurable partitions is something that is only supported in the flow with Abstract Shell.  
This is something we have not explored for composable.

If you would like to explore, you can find information here: [Create a new accelerator RM — Kria SOM DFX Examples 1.0 documentation](https://xilinx.github.io/kria-apps-docs/dfx/build/html/docs/creation_of_new_RM.html)  
This is something we do not support in this forum.

Mario

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 3:45pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/7 "2023-04-03T15:45:48Z")

</div>

Hi @marioruiz,

That’s no problem, I will have to do a bit of research on the abstract shell first.

Instead I am trying @jcollier’s method of replacing a static ip, but I am a bit confused at the "\*\*Build the vitis IP \*\* section, which surrounds the building of the makefile to sync the new cpp file in the src.

It’s not very clear in this example whether they are using a ZCU104 board or whether the vision\_ip code is held under the ZCU104 folder and this is where you access it.

I am using the KV260, do I just need to run the makefile that is under the KV260 folder, as I notice it contains reference to the vitis ip vision libraries

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fbd440913a0f63f306fb34f6380ab12910a732ff.png)

If so will this prompt the full Vivado procedure with the generation of all the files again?

Thanks,  
Cameron

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 3:54pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/8 "2023-04-03T15:54:41Z")

</div>

Realised just after I posted that I have to then link to that _vision\_ip_ heading in the KV260 makefile by running:

```auto
make vision_ip

```

within the kv260 folder.

Will see if it works.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 3, 2023, 4:06pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/9 "2023-04-03T16:06:36Z")

</div>

> [@cking](#):
>
> If so will this prompt the full Vivado procedure with the generation of all the files again?

Yes, to modify anything on the static portion you need to kick off the whole project build regardless of the flow.  
If you would like to add something on the dynamic part, you can do it manually with or without Abstract Shell.

Mario

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 4:12pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/10 "2023-04-03T16:12:39Z")

</div>

Hi Mario,

Wait, so I can add something to the dynamic (dfx) region manually without abstract shell, just as jcollier has done here by ip creation?

Thanks, Cameron

---

<div class="post-metadata">

**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\
**Post date:** [April 3, 2023, 4:21pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/11 "2023-04-03T16:21:40Z")

</div>

@cking

You can:  
Very easy:

> [@PYNQ 2.7 DFX Partial Reconfiguration under Vivado 2020.2](https://discuss.pynq.io/t/pynq-2-7-dfx-partial-reconfiguration-under-vivado-2020-2/4713):
>
> Hello all, Introduction Due to limited support on the modulator(s) about example of DFX and procedure. I will try to share the DFX on PYNQ 2.7 flow and method that I think it is working. The goal is to provide a simplest and easiest start of DFX on PR. No “composite overlay”, no other installation just PYNQ default API. First we are targeting Vivado 2020.2 not 2020.2.# which is the same build revision of the PYNQ on SD Image. So the first element is to make sure it is aligning both SD imag…

For 3.0 vivado 2022 you can make it even easier by block design container BDC.

ENJOY~

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 4:35pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/12 "2023-04-03T16:35:11Z")

</div>

Hi @marioruiz

I tried running the “make vision\_ip” code but it seems to present the following error and I’m at a bit of a loss.

Do you think this is another error presented due to the RAM of the system?

 ![vision_ip_error](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/afc9a5fe2d733d05a5b1d72e5146d5bc70fd0c82.jpeg)

p.s. I created the file on the left ‘rgb2bgr’ taking advantage of the rgb2bgr open cv tool in the vitis vision library, this is what I am trying to resync to the src folder loaded into vivado.

Any help appreciated,  
Thanks,  
Cameron

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 3, 2023, 4:39pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/13 "2023-04-03T16:39:27Z")

</div>

Thanks Brian will check it out!

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 3, 2023, 8:48pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/14 "2023-04-03T20:48:14Z")

</div>

The error is likely because the code has an error. You can try to open the Vitis project that gets generated an see if you can spot the error.

It also seems that the top level function doesn’t match the name of the file.

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 4, 2023, 10:49am UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/15 "2023-04-04T10:49:18Z")

</div>

Hi Mario,

Apologies for the pestering but still struggling to get the cpp code synced with the `make Vision_ip` command.

I have rewritten the cpp code for the rgb2bgr vision IP, However I’m still unsure how to know what to put in the file for #include, #define or the #pragmas. Is there a guide on building the cpp code required for functions in the vision IP library?

[rgb2bgr.cpp](https://discuss.pynq.io/uploads/short-url/fuJ8K8BxFnb7MeC7y5QqInviHAq.cpp) (1.5 KB)

This code still presents the error code 2. “no matching function to call 'rgb2bgr”

Any advice would be appreciated,  
Cameron

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 4, 2023, 11:30am UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/16 "2023-04-04T11:30:37Z")

</div>

Hi Cameron,

The Vitis Libraries are documented here [AMD Adaptive Computing Documentation Portal](https://docs.xilinx.com/r/en-US/Vitis_Libraries/vision/index.html)

You can look at the implementation details of the function here [Vitis\_Libraries/xf\_cvt\_color.hpp at main · Xilinx/Vitis\_Libraries · GitHub](https://github.com/Xilinx/Vitis_Libraries/blob/main/vision/L1/include/imgproc/xf_cvt_color.hpp#L7479)  
And detailed documentation here [AMD Adaptive Computing Documentation Portal](https://docs.xilinx.com/r/en-US/Vitis_Libraries/vision/api-reference.html_2_23_37)

Please, check that the datatypes your are using for the input and output images are correct and what the function expects.

Mario

---

<div class="post-metadata">

**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\
**Post date:** [April 4, 2023, 12:07pm UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/17 "2023-04-04T12:07:38Z")

</div>

@marioruiz

Should this converted to support label?  
I think learn label is more related to confirmed knowledge sharing?

ENJOY~

---

<div class="post-metadata">

**Author:** ![cking](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cking/32/5476_2.png) [@cking](https://discuss.pynq.io/u/cking)\
**Post date:** [April 5, 2023, 11:21am UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/18 "2023-04-05T11:21:27Z")

</div>

Hi Mario,  
Thanks for the links, with their help I was able to deduce the issue and get the .cpp file synthesised, with the IP block added to vivado replacing another in the static configuration.

I was hoping maybe you could elaborate on the exporting of the bitstream after generation. Do I have to manually carry out the block editing in the gui, followed by synth, impl and .bit generation or can I edit the makefile code to grab my desired .cpp (rgb2bgr) from the src folder rather than one (rgb2hsv) in the predefined static pipeline?

Following Jcollier’s steps for the Gui method, Is he gathering all of the files that would make up the “_overlay_” file that comes as a result of running the makefile (i.e. .bit .hwh .dtbo .json and all the partials) with the code under his " **collect the overlay files and package everything**"section?

As intuitively it looks like its just the tcl file he is gathering.

Sorry for the constant questioning!

Thanks,  
Cameron

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 5, 2023, 11:41am UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/19 "2023-04-05T11:41:45Z")

</div>

Hi Cameron,

> I was hoping maybe you could elaborate on the exporting of the bitstream after generation. Do I have to manually carry out the block editing in the gui, followed by synth, impl and .bit generation or can I edit the makefile code to grab my desired .cpp (rgb2bgr) from the src folder rather than one (rgb2hsv) in the predefined static pipeline?

This would be the easiest path, just update the tcl file to include your IP, and rerun the `Makefile`.

You can also do this from the GUI, but then you need to collect and rename all the necessary files manually.

Mario

---

<div class="post-metadata">

**Author:** ![juanppalacios](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/juanppalacios/32/5502_2.png) [@juanppalacios](https://discuss.pynq.io/u/juanppalacios)\
**Post date:** [June 3, 2024, 3:31am UTC](https://discuss.pynq.io/t/changing-the-ip-in-the-composable-pipeline/4301/20 "2024-06-03T03:31:55Z")

</div>

Hi,

I am looking to add a FINN stitched-IP to make use of the MIPI input / DP output pipeline. Does this guide still work for this proposed idea? Or is there an easier way to include a FINN-IP into the pipeline without having to do certain steps since we already have our .bit/.hwh files from FINN? I am aiming to deploy this on a Kria KV260 on PYNQ 3.0.1

Thanks!