# Common PL Devices on PYNQ

**URL:** <https://discuss.pynq.io/t/common-pl-devices-on-pynq/2815>\
**Category:** Learn\
**Created:** [July 6, 2021, 4:38pm UTC](https://discuss.pynq.io/t/common-pl-devices-on-pynq/2815 "2021-07-06T16:38:27Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Enrico\_Giordano](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/enrico_giordano/32/1352_2.png) [@Enrico\_Giordano](https://discuss.pynq.io/u/Enrico_Giordano)\
**Post date:** [July 6, 2021, 4:38pm UTC](https://discuss.pynq.io/t/common-pl-devices-on-pynq/2815/1 "2021-07-06T16:38:27Z")

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Dear all,  
we have prepared a github repository with common devices implemented in PL side of FPGA. In this repo we provide some tutorials to build in PL on PYNQ Z2 board 4 devices: GPIO, I2C, SPI, UART.

This is the repo:

> **[GitHub - MakarenaLabs/Common-PL-Devices-on-PYNQ: Integration on PL side of...](https://github.com/MakarenaLabs/Common-PL-Devices-on-PYNQ)**
>
> Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART) - GitHub - MakarenaLabs/Common-PL-Devices-on-PYNQ: Integration on PL side of Zynq7000 fo...

If you have suggestions, feel free to reply to this post.  
Thanks and happy acceleration!

Enrico Giordano - MakarenaLabs

> **[Home](https://www.makarenalabs.com/)**
>
> software development, AR/VR , game design, machine learning, digital signal processing, teaching and training courses, hardware acceleration

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<div class="post-metadata">

**Author:** ![Enrico\_Giordano](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/enrico_giordano/32/1352_2.png) [@Enrico\_Giordano](https://discuss.pynq.io/u/Enrico_Giordano)\
**Post date:** [July 27, 2021, 1:03pm UTC](https://discuss.pynq.io/t/common-pl-devices-on-pynq/2815/2 "2021-07-27T13:03:10Z")

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We have also write an article about this project:

> **[SPI, I2C, UART on PYNQ: a PL approach](https://www.makarenalabs.com/spi-i2c-uart-on-pynq-a-pl-approach/)**
>
> SPI, I2C and UART on PYNQ on PL side of Xilinx FPGA using Vivado block design, the complete pynq tutorial for generate bitstream
