# DAC / ADC exemple on ZCU111 **URL:** \ **Category:** Support\ **Created:** [August 20, 2020, 10:42am UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666 "2020-08-20T10:42:58Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![damien.fruleux](https://avatars.discourse-cdn.com/v4/letter/d/2acd7d/32.png) [@damien.fruleux](https://discuss.pynq.io/u/damien.fruleux)\ **Post date:** [August 20, 2020, 10:42am UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/1 "2020-08-20T10:42:58Z")
Hello 🙂 I need to learn how to use the DAC and ADC on a ZCU111 with Pynq. I create a simple design with a DMA to be able to read data from RAM to AXIS DAC and to write AXIS ADC data to RAM. More or less, it’s like Strathclyde’s QPSK project but very light and without QPSK. If I succeed, I will share my work on GitHub. I think some people speak about a similar project here ([RFSoC DAC with Pynq](https://discuss.pynq.io/t/rfsoc-dac-with-pynq/268)), but It never finished ? ---
**Author:** ![damien.fruleux](https://avatars.discourse-cdn.com/v4/letter/d/2acd7d/32.png) [@damien.fruleux](https://discuss.pynq.io/u/damien.fruleux)\ **Post date:** [August 20, 2020, 10:51am UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/2 "2020-08-20T10:51:42Z")
You can found my Vivado project here : [ZCU111-DAC-ADC-exemple.pdf](https://discuss.pynq.io/uploads/short-url/ev3wtoSYtfsrKITw5ruYl4jOAay.pdf) (240.2 KB) I add a constant for AXIS bus of write DMA, because _usp\_rf\_data\_converter_ IP not offer one. My jupyter notebook can be found here : [ZCU111-DAC-ADC-exemple.ipynb](https://discuss.pynq.io/uploads/short-url/mr4YOLzqSCvKevi8nRxqqzpW74k.ipynb) (4.2 KB) Thank you very much 🙂 Damien ---
**Author:** ![damien.fruleux](https://avatars.discourse-cdn.com/v4/letter/d/2acd7d/32.png) [@damien.fruleux](https://discuss.pynq.io/u/damien.fruleux)\ **Post date:** [September 16, 2020, 8:49am UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/3 "2020-09-16T08:49:04Z")
After reading a few documents, the constant is not a good idea. It is necessary to have a TLAST port for the DMA, and the ADC did not provide it. Probably it is necessary to use a custom IP to convert AXI STREAM without TLAST signal to AXI STREAM with TLAST signal ? Damien ---
**Author:** ![damien.fruleux](https://avatars.discourse-cdn.com/v4/letter/d/2acd7d/32.png) [@damien.fruleux](https://discuss.pynq.io/u/damien.fruleux)\ **Post date:** [October 16, 2020, 9:30am UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/4 "2020-10-16T09:30:33Z")
Hello, I post the question on Xilinx forum, and I found the solution for the TLAST here : [https://forums.xilinx.com/t5/Versal-and-UltraScale/TLAST-signal-with-Zynq-UltraScale-RFSoC-RFData-Converter-on/m-p/1156447#M14945](https://forums.xilinx.com/t5/Versal-and-UltraScale/TLAST-signal-with-Zynq-UltraScale-RFSoC-RFData-Converter-on/m-p/1156447#M14945) The DAC seem to work correctly but not the ADC for the moment. Damien ---
**Author:** ![A\_Jon](https://avatars.discourse-cdn.com/v4/letter/a/f04885/32.png) [@A\_Jon](https://discuss.pynq.io/u/A_Jon)\ **Post date:** [January 18, 2022, 3:11pm UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/5 "2022-01-18T15:11:27Z")
Hi Damien, Could you please share the .tcl script for your final vivado block design? ---
**Author:** ![jlanzuela](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jlanzuela/32/3328_2.png) [@jlanzuela](https://discuss.pynq.io/u/jlanzuela)\ **Post date:** [June 9, 2022, 12:28pm UTC](https://discuss.pynq.io/t/dac-adc-exemple-on-zcu111/1666/6 "2022-06-09T12:28:57Z")
Sorry, can you share your bitstream and hwh file with the project? Thank you Damien