# DAC bringup **URL:** \ **Category:** Support\ **Created:** [September 12, 2024, 10:38am UTC](https://discuss.pynq.io/t/dac-bringup/7482 "2024-09-12T10:38:00Z")\ **Posts on this page:** 10\ **Page:** 1
**Author:** ![jakkefire](https://avatars.discourse-cdn.com/v4/letter/j/8dc957/32.png) [@jakkefire](https://discuss.pynq.io/u/jakkefire)\ **Post date:** [September 12, 2024, 10:38am UTC](https://discuss.pynq.io/t/dac-bringup/7482/1 "2024-09-12T10:38:00Z")
Hi. I want to get started with RFSoC development and pynq (RFSoC4x2 board, pynq 3.0.1). I ran and studied the provided overlays but now i want to start using my own hardware. I created a minimal design, 1 DAC enabled, tile 230. ca 1GSPs. My clocks are connected and i verified the are OK. When i load the overlay i see the RFDC driver is getting loaded. But when i check the rfdc.IPStatus i see all my tiles report IsEnabled = 0. I tested multiple clock and reset sequences, but i don’t get this to work. Should i do some startup initialization on the pynq driver ? Any ideas how to start debugging this ? Thanks ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 13, 2024, 12:05am UTC](https://discuss.pynq.io/t/dac-bringup/7482/2 "2024-09-13T00:05:54Z")
Hi, Which error do you encounter? is it displayed? Or does your architecture freeze when it is not working as intended? ---
**Author:** ![jakkefire](https://avatars.discourse-cdn.com/v4/letter/j/8dc957/32.png) [@jakkefire](https://discuss.pynq.io/u/jakkefire)\ **Post date:** [September 13, 2024, 6:00am UTC](https://discuss.pynq.io/t/dac-bringup/7482/3 "2024-09-13T06:00:20Z")
Hi Matthew, thanks for your time. I am not getting any error message. Building the vivado design works without problems. Loading the overlay works as well. But nothing is output by the DAC, my datapath stalls (tReady remains low) and when polling the rfdc within pynq i get ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/5/57481ec566a48d024b369864a2df8643adc75a09.png) Since it is my first design with pynq and rfsoc i was wondering if i need to configure some things from within the pynq driver or not ? Yesterday evening i had a bit of a breakthrough: i need the rfdc to operate in DUC bypass mode to get the 9.8GSPs samplerate i am aiming for. I changed this to “DUC 0 to Fs/2” and now it comes to live. So at least i know now my pynq driver is ok. But my design still doesn’t work with datapath mode 4 (see pg269 page 132). If you have any idea on how to fix this i would love to hear it. Thanks. ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 13, 2024, 2:45pm UTC](https://discuss.pynq.io/t/dac-bringup/7482/4 "2024-09-13T14:45:34Z")
Can you please provide the block design, the architecture you are using? Can you also provide the code or notebook you use for controlling the DAC? I want to check how you activated the DAC. In the xilinx notebook for the xilinx architecture, they activated the DACs via: **for i in range(0, len(base.radio.transmitter.channel)):** **base.radio.transmitter.channel[i].control.gain = 0.5** **base.radio.transmitter.channel[i].control.enable = True** The notebook can be see here: ([RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01\_rf\_dataconverter\_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub](https://github.com/Xilinx/RFSoC-PYNQ/blob/master/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb)) How do you check the output of the DAC? By connecting it to an oscilloscope? ---
**Author:** ![jakkefire](https://avatars.discourse-cdn.com/v4/letter/j/8dc957/32.png) [@jakkefire](https://discuss.pynq.io/u/jakkefire)\ **Post date:** [September 16, 2024, 8:17am UTC](https://discuss.pynq.io/t/dac-bringup/7482/5 "2024-09-16T08:17:37Z")
Hey Matthew, i used a stripped down version of the rfsoc base overlay for my blockdesign, i generate data in an external module outside of the IPI block design. [blockdesign.pdf](https://discuss.pynq.io/uploads/short-url/vKpPmfObtFDW1kkvirDP8Non3gb.pdf) (242.6 KB) If i am correct then they created a ‘radio’ hierarchy which combines the RFDC ip core with a transmitter and receiver hierarchy to generate/record data. I tried to read through the xrfdc and rfsystem packages on the rfsoc board to see what happens during the initialization but as far as i can tell nothing needs to be enabled in the rfdc block (is this assumption correct) ? At least if you configured it according to your wishes in the vivado design. The control.enable = True only impacts the transmitter block to start generating data ? Or am i wrong and do i have to implement a startup routine in my pynq drivers ? Thanks again for your time. ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 16, 2024, 3:16pm UTC](https://discuss.pynq.io/t/dac-bringup/7482/6 "2024-09-16T15:16:59Z")
Can you please provide the code or notebook you use for controlling the DAC? I am not sure but I think you still need the control.enable to initialize the transmitter and receiver hierarchy to communicate with the DACs and ADCs. There is also a line **base.init\_rf\_clks()** in the base notebook, it says it initializes the clocks, but maybe it also launches the drivers. ---
**Author:** ![jakkefire](https://avatars.discourse-cdn.com/v4/letter/j/8dc957/32.png) [@jakkefire](https://discuss.pynq.io/u/jakkefire)\ **Post date:** [September 17, 2024, 7:21am UTC](https://discuss.pynq.io/t/dac-bringup/7482/7 "2024-09-17T07:21:51Z")
Hi Matthew, here is my relevant code: if have an overlay class > import os > import sys > from pynq import DefaultHierarchy > from pynq import DefaultIP > from pynq import Overlay > import xrfclk > import xrfdc > > class rfsocdriver(Overlay): > > ``` > def __init__ (self,bitfile=None, verbose:bool=True): > #Initialise the LMK and LMX clocks for the radio hierarchy. > xrfclk.set_ref_clks(lmk_freq=245.76, lmx_freq=491.52) > #program bitfile > if bitfile == None: bitfile = os.path.join(os.path.dirname( __file__ ), 'rfsoc.bit') > super(). __init__ (bitfile) > #select interfaces > self.rf = self.usp_rf_data_converter_0 > > ``` Then in my main notebook i call this class and probe the rf.IPStatus > import rfsocdriver > ol = rfsocdriver.rfsocdriver() > ol.rf.IPStatus But this doesn’t show any enabled tiles… I’m not using the radio hierarchy but am trying to control the rfdc directly. So the control.enable functions doesn’t even exists… ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 17, 2024, 12:57pm UTC](https://discuss.pynq.io/t/dac-bringup/7482/8 "2024-09-17T12:57:44Z")
If I understand correctly, you created a custom Vivado architecture. Where did you add your .bit and .hwh files in your RFSoC 4x2? ---
**Author:** ![jakkefire](https://avatars.discourse-cdn.com/v4/letter/j/8dc957/32.png) [@jakkefire](https://discuss.pynq.io/u/jakkefire)\ **Post date:** [September 23, 2024, 8:58am UTC](https://discuss.pynq.io/t/dac-bringup/7482/9 "2024-09-23T08:58:33Z")
My rfsocdriver class extends the basic Overlay class. That is where the bit and hwh file are loaded. I seem to have solved the problem by connecting the rfdc AXI interface to the FPD instead of the LPD in my original blockdesign. I’m not sure why this solved it, but for now i’m out of the bad water … Thanks. ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [September 23, 2024, 3:02pm UTC](https://discuss.pynq.io/t/dac-bringup/7482/10 "2024-09-23T15:02:16Z")