# Developing Verilog AXI Stream Overlays and interfacing to ZYNQ

**URL:** <https://discuss.pynq.io/t/developing-verilog-axi-stream-overlays-and-interfacing-to-zynq/1643>\
**Category:** Learn\
**Created:** [August 16, 2020, 1:04am UTC](https://discuss.pynq.io/t/developing-verilog-axi-stream-overlays-and-interfacing-to-zynq/1643 "2020-08-16T01:04:02Z")\
**Posts on this page:** 1\
**Showing post:** 6

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**Author:** ![RogerPease](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rogerpease/32/6592_2.png) [@RogerPease](https://discuss.pynq.io/u/RogerPease)\
**Post date:** [February 11, 2021, 1:21pm UTC](https://discuss.pynq.io/t/developing-verilog-axi-stream-overlays-and-interfacing-to-zynq/1643/6 "2021-02-11T13:21:15Z")

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Hi-

> [@Tutorial: Creating a new Verilog Module Overlay](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530/2):
>
> Great, thanks for sharing!

and

> [@Tutorial: Creating a Verilog Overlay with Bidirectional Pins](https://discuss.pynq.io/t/tutorial-creating-a-verilog-overlay-with-bidirectional-pins/1610):
>
> Building a Verilog overlay with Bidirectional pins Background This tutorial is targeted at users who wish to interface the PL of a Zynq 7000 and use pins as inputs, outputs or Bidirectional pins. This tutorial was developed on a TUL-2 Board… Other development boards may require modifications. Sample sources are linked. Use caution when selecting pins or applying drive values to pins as contending drivers (either from your board or you) can damage the part or the board. Also be sure to select pin…

Are the prior two tutorials I had written.

Roger

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