# DMA channel not IDLE error with custom IP

**URL:** <https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282>\
**Category:** Support\
**Created:** [July 16, 2024, 11:03pm UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282 "2024-07-16T23:03:40Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![rgbblue](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rgbblue/32/6124_2.png) [@rgbblue](https://discuss.pynq.io/u/rgbblue)\
**Post date:** [July 16, 2024, 11:03pm UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282/1 "2024-07-16T23:03:40Z")

</div>

I am trying to pass an array of numbers to the DMA and then add a number to each of them in the PL and then pass it back to the PS, however, I am getting a DMA channel not idle error, when I have put implemented logic for TLAST, TKEEP, TVALID and TREADY:

```auto
module adder#(parameter DATA_WIDTH=32, CAPACITY = 10)(
    // common signals
    input axi_clk,
    input axi_reset_n, // active low - as required by AXI protocol
    
    // AXI4-S slave interface
    input s_axis_valid, 
    input [DATA_WIDTH-1:0] s_axis_data,
    output s_axis_ready,
    
   // AXI4-S master interface 
    output reg m_axis_valid,
    output reg [DATA_WIDTH-1:0] m_axis_data,
    input m_axis_ready,
    output reg m_axis_t_last,
    output reg [3:0] m_axis_t_keep
    );
    
    reg [$clog2(CAPACITY):0] count;
    
    // when are we ready to accept data?
    // we are only streaming, so this slave is only ready if the master is ready
    assign s_axis_ready = m_axis_ready;
    
    always@(posedge axi_clk)
    begin 
        if(count < CAPACITY)
        begin
            m_axis_t_last <= 0;
        end
        else
        begin
            m_axis_t_last <= 1;
        end
    end
    
    always@(posedge axi_clk)
    begin
        if(s_axis_valid & s_axis_ready)
        begin
            m_axis_data <= m_axis_data + 32'b10100;
            count <= count + 1;
        end
    end
    
    always@(posedge axi_clk)
    begin
        m_axis_valid <= s_axis_valid & s_axis_ready;// valid data as output when we have valid data in input and already processed it - will come one clk after receiving the input valida data
        m_axis_t_keep <= 4'b1111;
    end
endmodule

```

For context, this is my block diagram:

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/9/9853ec0f24afd6617f30dcb471803c8adcfd9ca9.png)

And this is my notebook:

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/e12b0a3a92e2062be1193af07d871ec420ed303a.png)

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c9f2923e906e3fece983dc8623f548bc5c1a58b1.png)

I get this error having ran the cells multiple times, and I did get inconsistent outputs, albeit the outputs of one of the 10 numbers increased by 20 or 40 - still not all correct as I expect an array of 21s in the end - although I did initially pass an array of 1000 0s, so it could be that this is still being read or something - not too sure.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 17, 2024, 7:59am UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282/2 "2024-07-17T07:59:05Z")

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Hi @rgbblue,

I wrote a blog series describing common DMA issues.

> [@Debugging Common DMA Issues \[Part 3\]](https://discuss.pynq.io/t/debugging-common-dma-issues-part-3/7157):
>
> Debugging Common DMA Issues If you frequent the PYNQ forum, one of the most common questions/issues we get is why DMA transfer do not work. In part 3 of this series, I will reproduce these issues and use both the register\_map and ILA to identify and address these issues. DMA channel not started Often, we see users reporting something like this. --------------------------------------------------------------------------- RuntimeError Traceback (most recent call last) Input In [4], in \<cell line:…

Mario

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<div class="post-metadata">

**Author:** ![rgbblue](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rgbblue/32/6124_2.png) [@rgbblue](https://discuss.pynq.io/u/rgbblue)\
**Post date:** [July 17, 2024, 9:29am UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282/3 "2024-07-17T09:29:20Z")

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Hi, thank you for the link, I still can’t seem to solve the issue, I can receive some data - albeit incorrect data. As in I receive an array of 0s instead of 21s, then the first element becomes 240 and then increases by 20 and later 40 each time. Then after a few runs - when the first element is 500, i get the channel not idle issue. I’m still not sure why this is the case.

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [July 17, 2024, 3:17pm UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282/4 "2024-07-17T15:17:03Z")

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You indicated that you have designed your own HDL module, so I suggest you verify that this module is handling the AXI4-Stream channel correctly.

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<div class="post-metadata">

**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\
**Post date:** [August 9, 2024, 3:09am UTC](https://discuss.pynq.io/t/dma-channel-not-idle-error-with-custom-ip/7282/5 "2024-08-09T03:09:29Z")

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Hi,  
Have you tried with another value of data\_size, like 200?