# DMA error in DAC-ADC loopback

**URL:** <https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773>\
**Category:** Support\
**Created:** [July 4, 2023, 1:55pm UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773 "2023-07-04T13:55:46Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![mselva2](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mselva2](https://discuss.pynq.io/u/mselva2)\
**Post date:** [July 4, 2023, 1:55pm UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/1 "2023-07-04T13:55:46Z")

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PYNQ Version: PYNQ 2.7.0  
Board: ZCU111  
Error: DMA channel not started  
ADC : ADC224\_T0\_CH0  
DAC: DAC229\_T1\_CH2

Problem Description:  
I want to do DAC-ADC loopback in ZCU111 board. So, I generated sinusoidal signal of 8192 samples, and transferred to DAC via DMA. In receiver side, the samples from ADC are stored in DDR via DMA.  
But I am getting error “DMA channel not started”

I have attached tcl file and python file.

Please help me resolve this problem.  
[dac\_adc\_loopback.ipynb](https://discuss.pynq.io/uploads/short-url/pWDIs2YwvCeDoOlcYanewQUDyI9.ipynb) (20.9 KB)  
[dac\_adc\_loopback.tcl](https://discuss.pynq.io/uploads/short-url/sZ5UPpjLM8RQsNqlYc06hHlP0Ri.tcl) (24.2 KB)

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<div class="post-metadata">

**Author:** ![mselva2](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mselva2](https://discuss.pynq.io/u/mselva2)\
**Post date:** [July 4, 2023, 2:01pm UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/2 "2023-07-04T14:01:03Z")

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I am also attaching hwh file and DMA configuration screenshot.  
[dac\_adc\_loopback.hwh](https://discuss.pynq.io/uploads/short-url/1QcUN0PJycVxVl16XhrckTXJBX1.hwh) (592.9 KB)

 ![DMA_Configuration](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/d/d38f60d807156f0d6079d1cdc5ef7aa83bdbd1fd.jpeg)

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<div class="post-metadata">

**Author:** ![mselva2](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mselva2](https://discuss.pynq.io/u/mselva2)\
**Post date:** [July 4, 2023, 2:02pm UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/3 "2023-07-04T14:02:47Z")

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ADC & DAC clock configuration

 ![Clock](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/9/90c55a021b8ad93c2b9b5100c87c6ea69f16b09d.jpeg)

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [July 4, 2023, 4:22pm UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/4 "2023-07-04T16:22:30Z")

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You may have the same issue with “TLAST” as this post: [Zynq Ultrascal+ RF data Converter to DMA - #4 by cathalmccabe](https://discuss.pynq.io/t/zynq-ultrascal-rf-data-converter-to-dma/5735/4)

Cathal

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<div class="post-metadata">

**Author:** ![mselva2](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mselva2](https://discuss.pynq.io/u/mselva2)\
**Post date:** [July 7, 2023, 9:15am UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/5 "2023-07-07T09:15:56Z")

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Thanks Cathal, with tlast generation module it is working

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<div class="post-metadata">

**Author:** ![Pavithra\_B\_S](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/pavithra_b_s/32/7564_2.png) [@Pavithra\_B\_S](https://discuss.pynq.io/u/Pavithra_B_S)\
**Post date:** [July 27, 2026, 6:46am UTC](https://discuss.pynq.io/t/dma-error-in-dac-adc-loopback/5773/6 "2026-07-27T06:46:17Z")

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hey, Did you just add the tlast\_generator module from the pynq\_nco design? or did u create your custom module..I am facing the same issue and am not sure how to add it.