# DMA for xc70z030fbg676-1 not working!

**URL:** <https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548>\
**Category:** Support\
**Created:** [April 14, 2021, 5:42am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548 "2021-04-14T05:42:12Z")\
**Posts on this page:** 9\
**Page:** 1

<div class="post-metadata">

**Author:** ![akarsh](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@akarsh](https://discuss.pynq.io/u/akarsh)\
**Post date:** [April 14, 2021, 5:42am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/1 "2021-04-14T05:42:12Z")

</div>

HI all,

I have tried DMA example for PYNQ Z2 board, and it is working !!!

**Test setup**

1. We are trying the same example with the custom board ( **xc70z030fbg676-1** ) SOC.  
2)Pynq version - 2.6.0
2. VIvado -2020.1  
4)Vitis 2020.1
3. Petta Linux-2020.1

**Problem Statement**

1. I’am able to send the data through DMA and the status register says 400bytes are transfered.  
2)When i try to read back the same data through DMA **Error pops up saying DMA channel not started.**

Example design Link :  
[https://pynq.readthedocs.io/en/v2.4/pynq\_libraries/dma.html](https://pynq.readthedocs.io/en/v2.4/pynq_libraries/dma.html)

[design\_1.pdf](https://discuss.pynq.io/uploads/short-url/g4H4zBsxoU7MrFISU4qCsvkoV5a.pdf) (118.1 KB)  
 ![pynq_dma_error (1)](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/cab8a09c41e2ec6c3792d681c6ec040ab8a57832.png)

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<div class="post-metadata">

**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [April 14, 2021, 6:19am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/2 "2021-04-14T06:19:49Z")

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I don’t see a DMA in the block diagram for the design you posted (pdf).

The image is too small to read the code. Could you please repost a larger image or the error message that you see?

Cathal

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<div class="post-metadata">

**Author:** ![akarsh](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@akarsh](https://discuss.pynq.io/u/akarsh)\
**Post date:** [April 14, 2021, 7:02am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/3 "2021-04-14T07:02:51Z")

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Hi Cathal,

I have attached a block diagram with DMA and also cropped the error message.Please find the attachment.

Regards  
Akarsh  
[ps.pdf](https://discuss.pynq.io/uploads/short-url/l4pKsTGLfkFJ1rjrT2vX10KNqQC.pdf) (80.3 KB)

 ![pynq_dma_error (1)](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/e8d8daa105fc38479d97c3f0c80cc3a0fe1dec27.png)

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [April 14, 2021, 8:29am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/4 "2021-04-14T08:29:21Z")

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Would you be able to provide the output of `dma_fifo.register_map`?

Peter

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<div class="post-metadata">

**Author:** ![akarsh](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@akarsh](https://discuss.pynq.io/u/akarsh)\
**Post date:** [April 14, 2021, 9:38am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/5 "2021-04-14T09:38:59Z")

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Hello Peter,

I please find the register map

RegisterMap { MM2S\_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic\_BD\_Enable=0, IOC\_IrqEn=0, Dly\_IrqEn=0, Err\_IrqEn=0, IRQThreshold=1, IRQDelay=0), MM2S\_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=1, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC\_Irq=1, Dly\_Irq=0, Err\_Irq=1, IRQThresholdSts=0, IRQDelaySts=0), MM2S\_CURDESC = Register(Current\_Descriptor\_Pointer=0), MM2S\_CURDESC\_MSB = Register(Current\_Descriptor\_Pointer=0), MM2S\_TAILDESC = Register(Tail\_Descriptor\_Pointer=0), MM2S\_TAILDESC\_MSB = Register(Tail\_Descriptor\_Pointer=0), MM2S\_SA = Register(Source\_Address=939810816), MM2S\_SA\_MSB = Register(Source\_Address=0), MM2S\_LENGTH = Register(Length=400), SG\_CTL = Register(SG\_CACHE=0, SG\_USER=0), S2MM\_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic\_BD\_Enable=0, IOC\_IrqEn=0, Dly\_IrqEn=0, Err\_IrqEn=0, IRQThreshold=1, IRQDelay=0), S2MM\_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC\_Irq=1, Dly\_Irq=0, Err\_Irq=0, IRQThresholdSts=0, IRQDelaySts=0), S2MM\_CURDESC = Register(Current\_Descriptor\_Pointer=0), S2MM\_CURDESC\_MSB = Register(Current\_Descriptor\_Pointer=0), S2MM\_TAILDESC = Register(Tail\_Descriptor\_Pointer=0), S2MM\_TAILDESC\_MSB = Register(Tail\_Descriptor\_Pointer=0), S2MM\_DA = Register(Destination\_Address=0), S2MM\_DA\_MSB = Register(Destination\_Address=0), S2MM\_LENGTH = Register(Length=0) }

Regards  
Akarsh

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<div class="post-metadata">

**Author:** ![akarsh](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@akarsh](https://discuss.pynq.io/u/akarsh)\
**Post date:** [April 14, 2021, 9:40am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/6 "2021-04-14T09:40:06Z")

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Hi Peter

Please find the register map

```auto
RegisterMap {
  MM2S_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
  MM2S_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=1, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=1, IRQThresholdSts=0, IRQDelaySts=0),
  MM2S_CURDESC = Register(Current_Descriptor_Pointer=0),
  MM2S_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
  MM2S_TAILDESC = Register(Tail_Descriptor_Pointer=0),
  MM2S_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
  MM2S_SA = Register(Source_Address=939810816),
  MM2S_SA_MSB = Register(Source_Address=0),
  MM2S_LENGTH = Register(Length=400),
  SG_CTL = Register(SG_CACHE=0, SG_USER=0),
  S2MM_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
  S2MM_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=0, IRQThresholdSts=0, IRQDelaySts=0),
  S2MM_CURDESC = Register(Current_Descriptor_Pointer=0),
  S2MM_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
  S2MM_TAILDESC = Register(Tail_Descriptor_Pointer=0),
  S2MM_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
  S2MM_DA = Register(Destination_Address=0),
  S2MM_DA_MSB = Register(Destination_Address=0),
  S2MM_LENGTH = Register(Length=0)
}

```

```auto

```

```auto
Regards 

```

```auto
Akarsh 

```

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [April 14, 2021, 9:55am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/7 "2021-04-14T09:55:53Z")

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The send channel is showing a decode error - can you make sure that the PS’s DDR address space is correctly assigned for the DMA in the address editor in Vivado.

The receive channel isn’t showing any activity which is slightly weird. Hopefully the addressing is the problem for both

Peter

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<div class="post-metadata">

**Author:** ![akarsh](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@akarsh](https://discuss.pynq.io/u/akarsh)\
**Post date:** [April 14, 2021, 10:35am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/8 "2021-04-14T10:35:54Z")

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Hi Peter,

I have attached the Address space of DMA in vivado to this email.Please find the attachment.  
Can you please suggest what changes need to be done?

Regards  
AKarsh

 ![address_spcae.png](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/d/d77e50f30200b2bb93a157ec9d67af50a6d6cdb4.png)

Akarsh

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [April 14, 2021, 10:48am UTC](https://discuss.pynq.io/t/dma-for-xc70z030fbg676-1-not-working/2548/9 "2021-04-14T10:48:49Z")

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Your base addresses for the HP0\_DDR\_LOWOCM need to be 0 and have a range of 512 MB

Peter