# DMA IP cause Jupyter notebook kernel dying **URL:** \ **Category:** Support\ **Created:** [June 6, 2024, 6:10pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112 "2024-06-06T18:10:32Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 6, 2024, 6:10pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/1 "2024-06-06T18:10:32Z")
I’ve been using PYNQ v2.7 and Vivado 2020.2, and I’ve encountered an issue where initializing the DMA IP causes the Jupyter Notebook kernel to die. The command I’m using to initialize the DMA is `dma = ol.qpsk_rx.dma`. Despite having already inserted the `tlast` signal to notify the DMA, the kernel still crashes. Could anyone help me understand the reason behind this issue and suggest how I might fix it? Below is the setting about DMA and FIFO: ![Screenshot 2024-06-06 140837](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/2a06ad3b6334da040a6c7f4fafa1186ca0f544ee.png) ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/d/db76ff87dd621e24b502a8fde0bf050757d37743.jpeg) ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/ea39412883247efc23d42829da60324e34e6a28f.png) Thank you! ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 6, 2024, 10:55pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/2 "2024-06-06T22:55:43Z")
Out of curiosity, do you still have the issue if you rename the “dma” element, by modifying your code into: **dma\_personal = ol.qpsk\_rx.dma**? What is ol in your code? ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 7, 2024, 10:21am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/3 "2024-06-07T10:21:24Z")
hi, I have already fixed the problem and a new problem happened. when i used the rx dma to receive signal, it appears “RuntimeError: DMA channel not started” ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c07a69b511786041514bea7e812d666ded66f304.png) but i have already generated the tlast signal, i used a counter to count ready signal did you know how to fix the issue? Thank you! ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 7, 2024, 1:18pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/4 "2024-06-07T13:18:15Z")
What is the size of the buffer\_rx you want to transmit? This issue can occur when the size of the buffer is lower or higher than your DMA size requirement. ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 7, 2024, 2:01pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/5 "2024-06-07T14:01:02Z")
The DMA’s buffer length setting is 26 bits, and I am transmitting 4096 pieces of 32-bit data. The send channel works fine, but the receive channel fails. So I don’t know why the recvchannel fail Thank you! ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 7, 2024, 2:31pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/6 "2024-06-07T14:31:30Z")
Can you try sending more or less of these pieces, like 500 or 7000? ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 8, 2024, 12:13pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/7 "2024-06-08T12:13:49Z")
I tried using 1024 pieces, but the result is still the same. ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 8, 2024, 8:20pm UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/8 "2024-06-08T20:20:47Z")
Did you try to send more pieces, like 8192 pieces? ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 10, 2024, 7:36am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/9 "2024-06-10T07:36:47Z")
Hi @pynqishard, Can you please post the full code where you send and receive data? Can you also check the dma register map? ```python dma.register_map ``` Mario ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 6:00am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/10 "2024-06-11T06:00:40Z")
Here is the dma.register\_map result ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/b/b7b9f6cb19f8ed19e3b4938c28f2d63b7cb3494b.jpeg) and the following is the code i used to send and receive data ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fd4ac27566832ca9b717279e9e6da767018c8a39.jpeg) Thank you ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 11, 2024, 7:52am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/11 "2024-06-11T07:52:54Z")
Hi @pynqishard, A few things, the FIFO is configured in packet mode, this means that before streaming data via the `M_AXIS` interface, it needs to receive all data until it is marked with the tlast bit. The depth is 512, so it can only contain, 512 elements of your complex numbers. You can try increasing the depth, or removing packet mode. I would also suggest you try removing the IP axis\_bypass to make sure this works before you add your custom logic. The dma register map you’re showing looks like it was run before the actual data transfer. Also, you’re mixing alias with full path to the IP, if you get an alias, for instance `tx_ch0`, I suggest you always use the alias even for the data transfer. A more pythonic way of creating the array of complex number is something like this: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/253e377f310ac85aa1e419590cd0294a977363d4.png) [Data type objects (dtype) — NumPy v1.26 Manual](https://numpy.org/doc/stable/reference/arrays.dtypes.html#dtype) (example just above this heading) Mario ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 8:23am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/12 "2024-06-11T08:23:11Z")
hi, I increase the FIFO depth to 8192 and the tlast bit will be asserted to ‘1’ when the counter counts m\_axis\_tready & m\_axis\_tvalid to 254. The new register map after running data transfer is below: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/058c4245a11d6d781a7fcd93ea25f2d317b0eba6.jpeg) ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/1b7642b8415d6ec03c46633341c42c2175af3148.jpeg) and I changed the full path to the alias I declaired before Thank you ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 11, 2024, 8:29am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/13 "2024-06-11T08:29:25Z")
Hi @pynqishard, I suggest you remove the axis\_bypass and to make sure the rest of the infrastructure works. I have seen this issue when tkeep is not properly handled. Mario ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 9:08am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/14 "2024-06-11T09:08:05Z")
hi, the function of axis\_bypass is to asser tlast to 1 and tkeep to 4’b1111 sorry, if the module name will make you confused. if i remove it, i get the same result when i run the code in the first time, it will stuck at rx.wait ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/7/7b6d991cc2431169b2260378a5ebf87368a979ef.jpeg) and next time i execute the code it will show DMA channel not idle ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 9:15am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/15 "2024-06-11T09:15:46Z")
> [@marioruiz](#): > > I have seen this issue when tkeep is not properly handled. Can the Tkeep to be assigned 4’b1111 all the time? ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 11, 2024, 9:31am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/16 "2024-06-11T09:31:03Z")
I am confused, what is the input to the rx dma IP, before the FIFO? > Can the Tkeep to be assigned 4’b1111 all the time? For the DMA , it can be. ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 9:34am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/17 "2024-06-11T09:34:14Z")
Hi, it’s the rf data converter output ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/82b3b87eef545ad23bc67d5af5aa0104ef293384.png) thank you! ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 11, 2024, 9:38am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/18 "2024-06-11T09:38:49Z")
Which design are you using as starting point? ---
**Author:** ![pynqishard](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pynqishard](https://discuss.pynq.io/u/pynqishard)\ **Post date:** [June 11, 2024, 10:07am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/19 "2024-06-11T10:07:45Z")
![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/33cbbde8ebc2b2101b611e29949933d45559cb6c.png) I allocated a register in the DDR memory. The AXI interface will transfer data from the DDR memory to the DMA\_TX, which will then serve as input to the RF Data Converter IP thanks! ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 11, 2024, 10:33am UTC](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112/20 "2024-06-11T10:33:24Z")
@pynqishard, it is becoming challenging to follow. Can please you let me know if you use any of the open source projects as starting point and if so which one (please provide link)? Then what modifications did you make to it? [Next page](https://discuss.pynq.io/t/dma-ip-cause-jupyter-notebook-kernel-dying/7112.md?page=2)