# DMA sends and receives multiple times

**URL:** <https://discuss.pynq.io/t/dma-sends-and-receives-multiple-times/6238>\
**Category:** Support\
**Created:** [October 27, 2023, 7:37am UTC](https://discuss.pynq.io/t/dma-sends-and-receives-multiple-times/6238 "2023-10-27T07:37:30Z")\
**Posts on this page:** 1\
**Showing post:** 4

<div class="post-metadata">

**Author:** ![j\_pynq](https://avatars.discourse-cdn.com/v4/letter/j/b2d939/32.png) [@j\_pynq](https://discuss.pynq.io/u/j_pynq)\
**Post date:** [October 30, 2023, 6:14pm UTC](https://discuss.pynq.io/t/dma-sends-and-receives-multiple-times/6238/4 "2023-10-30T18:14:34Z")

</div>

Hi,  
I was following [Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344)

My source code is based on [https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using\_axi\_stream\_with\_side\_channel\_data/example.cpp](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp)

```c
#include "ap_axi_sdata.h"
#include "hls_stream.h"

void example(hls::stream< ap_axis<32,2,5,6> > &A,
	     hls::stream< ap_axis<32,2,5,6> > &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma hls interface s_axilite port=return

	ap_axis<32,2,5,6> tmp;
    while(1)
    {
	A.read(tmp);
	tmp.data = tmp.data.to_int() + 5;
	B.write(tmp);
     if(tmp.last)
     {
         break;
     }
    }
    

}

```

You can also see the TLAST signal had been sythesised

 ![Screenshot 2023-10-30 at 20.13.14](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fc58419acb61e61bbfa9572a23b4385724ea19fe.png)

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