# Dynamic PR + DRAM access failure

**URL:** <https://discuss.pynq.io/t/dynamic-pr-dram-access-failure/2872>\
**Category:** Support\
**Created:** [July 26, 2021, 3:27pm UTC](https://discuss.pynq.io/t/dynamic-pr-dram-access-failure/2872 "2021-07-26T15:27:53Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![gabrielrodcanal](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/gabrielrodcanal/32/2280_2.png) [@gabrielrodcanal](https://discuss.pynq.io/u/gabrielrodcanal)\
**Post date:** [July 26, 2021, 3:27pm UTC](https://discuss.pynq.io/t/dynamic-pr-dram-access-failure/2872/1 "2021-07-26T15:27:53Z")

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Hello everyone,  
I have a Vivado design in which I have an HLS accelerator that accesses DRAM memory through an m\_axi interface with slave offset. DRAM is made available to the accelerator through the HP0 port in the Zynq CPU. This works fine with the full bitstream. However, once I program the FPGA with a partial bitstream the accelerator becomes unresponsive (ap\_start stays at 1 and there is no output). This gets solved when I program the FPGA with a full bitstream again.

The design is as follows:

I was wondering if this had something to do with how I am decoupling the m\_axi port, but it has worked before with similar designs and whenever there was a problem with decoupling the whole FPGA blocked, whereas here the pblock that is not reconfigured by the partial bitstream remains usable (this applies when I extend the design to two pblocks).

Just to clarify, this exact same design has worked before with partial reconfiguration when the interface of the HLS accelerators comprised only s\_axilite ports. I’m working with PYNQ-Z2.

The kernels I’m instantiating are at pblock 0 are:

```auto
#define SIZE_IN 10
#define SIZE_OUT 10

void add(int input[SIZE_IN], int output[SIZE_OUT]){
	#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
	#pragma HLS INTERFACE m_axi offset=slave port=input 
	#pragma HLS INTERFACE s_axilite port=input bundle=CTRL_BUS
	#pragma HLS INTERFACE m_axi offset=slave port=output
	#pragma HLS INTERFACE s_axilite port=output bundle=CTRL_BUS
	
	for(int i = 0; i < SIZE_IN; i++)
		output[i] = input[i] + 10;
}

```

and

```auto

#define SIZE_IN 10
#define SIZE_OUT 10

void add(int input[SIZE_IN], int output[SIZE_OUT]){
	#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
	#pragma HLS INTERFACE m_axi offset=slave port=input 
	#pragma HLS INTERFACE s_axilite port=input bundle=CTRL_BUS
	#pragma HLS INTERFACE m_axi offset=slave port=output
	#pragma HLS INTERFACE s_axilite port=output bundle=CTRL_BUS
	
	for(int i = 0; i < SIZE_IN; i++)
		output[i] = input[i] + 20;
}

```

Thank you.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3d3085e42c39a923c5f8d82250fb24c809b8369d.jpeg)

Edit:  
I’ve attached a simplified a design so it’s easier to find the answer.

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<div class="post-metadata">

**Author:** ![gabrielrodcanal](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/gabrielrodcanal/32/2280_2.png) [@gabrielrodcanal](https://discuss.pynq.io/u/gabrielrodcanal)\
**Post date:** [August 23, 2021, 11:25pm UTC](https://discuss.pynq.io/t/dynamic-pr-dram-access-failure/2872/2 "2021-08-23T23:25:09Z")

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Still haven’t found the cause to this issue. Could please someone share if they have came across the same problem? Is this some sort of bug?

P.D: I’m working with the PYNQ 2.4 image.

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<div class="post-metadata">

**Author:** ![luwawa](https://avatars.discourse-cdn.com/v4/letter/l/5fc32e/32.png) [@luwawa](https://discuss.pynq.io/u/luwawa)\
**Post date:** [September 20, 2022, 1:49am UTC](https://discuss.pynq.io/t/dynamic-pr-dram-access-failure/2872/3 "2022-09-20T01:49:11Z")

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Have you solved this problem?