# Failed to find axi\_dma\_0 and custom HLS IP core in Tysom board PYNQ **URL:** \ **Category:** Support\ **Created:** [August 4, 2025, 6:54am UTC](https://discuss.pynq.io/t/failed-to-find-axi-dma-0-and-custom-hls-ip-core-in-tysom-board-pynq/8662 "2025-08-04T06:54:32Z")\ **Posts on this page:** 1\ **Showing post:** 5
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 5, 2025, 7:36am UTC](https://discuss.pynq.io/t/failed-to-find-axi-dma-0-and-custom-hls-ip-core-in-tysom-board-pynq/8662/5 "2025-08-05T07:36:04Z")
> [@harivan](#): > > Now after making these changes, my pynq code is detecting zynq ps, axi dma, hls ip core, but it does not show other IPs like smart connect etc. Is this expected. Yes, this is correct. These IP cores are not memory mapped. > And the dma gets stuck before giving response output from HLS IP. I wrote an extensible debugging blog about this. Please check it > [@Debugging Common DMA Issues \[Part 3\]](https://discuss.pynq.io/t/debugging-common-dma-issues-part-3/7157): > > Debugging Common DMA Issues If you frequent the PYNQ forum, one of the most common questions/issues we get is why DMA transfer do not work. In part 3 of this series, I will reproduce these issues and use both the register\_map and ILA to identify and address these issues. DMA channel not started Often, we see users reporting something like this. --------------------------------------------------------------------------- RuntimeError Traceback (most recent call last) Input In [4], in \ In the attached MMIO is found missing, what is the fix , kindly help. This is related to the DMA issue Your original issue is resolved. I would suggest you create another topic for the DMA issue, only if the debugging blog is not enough. --- _[View the full topic](https://discuss.pynq.io/t/failed-to-find-axi-dma-0-and-custom-hls-ip-core-in-tysom-board-pynq/8662)._