# Help Building Pynq 2.7 for Ultra96v2

**URL:** <https://discuss.pynq.io/t/help-building-pynq-2-7-for-ultra96v2/4369>\
**Category:** Support\
**Created:** [June 20, 2022, 10:58pm UTC](https://discuss.pynq.io/t/help-building-pynq-2-7-for-ultra96v2/4369 "2022-06-20T22:58:35Z")\
**Posts on this page:** 1\
**Showing post:** 12

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**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\
**Post date:** [July 15, 2022, 3:08am UTC](https://discuss.pynq.io/t/help-building-pynq-2-7-for-ultra96v2/4369/12 "2022-07-15T03:08:00Z")

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Zen,

I appreciate the work but it will be highly suggest to verify the flow and do build success before merging.  
Meantime, I think the current virtual env just need to make it ready as good as possible. Shown [here](https://discuss.pynq.io/t/pynq-v2-7-sd-image-build-fail-for-board-pynq-z2/4243/50).

And even Ultra-Zynq just need to pay a bit attention to the dtsl config.  
As issue resolved [here](https://discuss.pynq.io/t/ultrazynq-build/4404/4)

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