# How could we use a axi interface in pynq? **URL:** \ **Category:** Support\ **Created:** [December 20, 2020, 11:58am UTC](https://discuss.pynq.io/t/how-could-we-use-a-axi-interface-in-pynq/2161 "2020-12-20T11:58:09Z")\ **Posts on this page:** 1\ **Showing post:** 4
**Author:** ![RogerPease](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rogerpease/32/6592_2.png) [@RogerPease](https://discuss.pynq.io/u/RogerPease)\ **Post date:** [December 20, 2020, 9:48pm UTC](https://discuss.pynq.io/t/how-could-we-use-a-axi-interface-in-pynq/2161/4 "2020-12-20T21:48:15Z")
If you want to do this in Verilog I did a few tutorials on this in the Learn area: > [@Tutorial: Creating a new Verilog Module Overlay](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530): > > This is a tutorial targeted at Verilog and Python users who wish to use Zynq 7000 to do Verilog FPGA module development and interface their Verilog in the PL to the PS system. I went through this learning curve a few months ago and wanted to share my experience to “pay it forward”. I used a [TUL-2](http://www.tul.com.tw/ProductsPYNQ-Z2.html) Board. Design Steps and decisions The general flow of design steps I followed are: Develop the IP. You will interface to your IP through a memory mapped interface. Instance the IP in an AXI IP Wrappe… > [@Tutorial: Creating a Verilog Overlay with Bidirectional Pins](https://discuss.pynq.io/t/tutorial-creating-a-verilog-overlay-with-bidirectional-pins/1610): > > Building a Verilog overlay with Bidirectional pins Background This tutorial is targeted at users who wish to interface the PL of a Zynq 7000 and use pins as inputs, outputs or Bidirectional pins. This tutorial was developed on a TUL-2 Board… Other development boards may require modifications. Sample sources are linked. Use caution when selecting pins or applying drive values to pins as contending drivers (either from your board or you) can damage the part or the board. Also be sure to select pin… --- _[View the full topic](https://discuss.pynq.io/t/how-could-we-use-a-axi-interface-in-pynq/2161)._