# How to compile custom overlay with integrated DPU on pynq

**URL:** <https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495>\
**Category:** Support\
**Created:** [December 29, 2023, 4:33pm UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495 "2023-12-29T16:33:35Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![tallgeeze](https://avatars.discourse-cdn.com/v4/letter/t/d9b06d/32.png) [@tallgeeze](https://discuss.pynq.io/u/tallgeeze)\
**Post date:** [December 29, 2023, 4:33pm UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495/1 "2023-12-29T16:33:35Z")

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Hi dear PYNQ community,

I have to integrate Xilinx DPU ip core into an exisiting vivado overlay(a system for some signal processing), which means: I have to first integrate the dpu into an exisiting blockdiagram in vivado(already solved), and then run such system with DPU in pynq and jupyter-notebook environment for later work. What is the general process of such requirement?

Since Pynq-dpu offers the bitsteam with reference dpu layout only, and vivado DPU workflow requires petalinux bootimage ( i am not so sure if installing pynq on petalinux is a good idea.), i am completely lost of ideas. Could anyone give me some insights about the workflow?

P.S: The reason that i could not directly use vivado to compile and generate the bitstream for such system is: the vivado will not generate .xclbin file, which is essential for pynq-dpu package to load with DpuOverlay(“custom\_overlay.bit”). Also the vitis-AI can only offer DPU overlay with custom setup, which is not what I looking for. I need an Overlay with DPU ip core included to work wtih exisiting signal processing system.

Thank you so much in advance !!

Current environment

- PYNQ 3.5 and ZYNQ-ZU board from TUL or ZCU104

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**Author:** ![Poulami](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/poulami/32/5822_2.png) [@Poulami](https://discuss.pynq.io/u/Poulami)\
**Post date:** [April 30, 2024, 8:48am UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495/2 "2024-04-30T08:48:08Z")

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Hey [@tallgeeze](https://discuss.pynq.io/u/tallgeeze) , did you solve this problem already? I am also facing the similar issue ! If possible, can we discuss it in details?

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**Author:** ![chim20air](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/chim20air/32/6795_2.png) [@chim20air](https://discuss.pynq.io/u/chim20air)\
**Post date:** [March 26, 2025, 8:15pm UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495/3 "2025-03-26T20:15:45Z")

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Now we are 3 with the same issues. I’ve got some ideas of how to generate the bitstreams. The thing is that I cannot load it to the DpuOverlay without errors.  
Here are 2 sources, I am not sure which will be a better option for this  
[[AMD Technical Information Portal](https://docs.amd.com/r/en-US/pg338-dpu/DPU-Configuration)](AMD PG338)  
https://www.fpga-radar.com/vivado-hw-dpu

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**Author:** ![tallgeeze](https://avatars.discourse-cdn.com/v4/letter/t/d9b06d/32.png) [@tallgeeze](https://discuss.pynq.io/u/tallgeeze)\
**Post date:** [March 28, 2025, 12:56pm UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495/4 "2025-03-28T12:56:57Z")

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Hello @Poulami @chim20air. Thank you for asking.  
Basically, to integrate DPU ip core in self-built custom overlay could be concluded as a vivado workflow of vitis-ai. Please refer to these link: [Creating a DPU-Compatible Platform for PYNQ - MakarenaLabs](https://www.makarenalabs.com/creating-a-dpu-compatible-platform-for-pynq/)  
and : [Vitis-Tutorials/Vitis\_Platform\_Creation/Design\_Tutorials/02-Edge-AI-ZCU104/step1.md at 2024.2 · Xilinx/Vitis-Tutorials · GitHub](https://github.com/Xilinx/Vitis-Tutorials/blob/2024.2/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step1.md)

As well the DPU-PYNQ official github would provide you a makefile to build dpu-contained overlay on a vitis-platform.

Such a workflow turns out to be the easiest way to deploy dpu in PYNQ environment.

GLHF

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**Author:** ![chim20air](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/chim20air/32/6795_2.png) [@chim20air](https://discuss.pynq.io/u/chim20air)\
**Post date:** [March 28, 2025, 4:22pm UTC](https://discuss.pynq.io/t/how-to-compile-custom-overlay-with-integrated-dpu-on-pynq/6495/5 "2025-03-28T16:22:43Z")

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Question, Are you using SV/verilog/VHDL code? or are you using HLS?