# How to connect custom HLS IP to Zynq board

**URL:** <https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139>\
**Category:** Support\
**Created:** [April 14, 2020, 2:16pm UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139 "2020-04-14T14:16:43Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![youn123](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/youn123/32/416_2.png) [@youn123](https://discuss.pynq.io/u/youn123)\
**Post date:** [April 14, 2020, 2:16pm UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/1 "2020-04-14T14:16:43Z")

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I’m new to PYNQ board, but my goal is very straightforward: do a matrix multiplication using the pynq board.

I have an IP created using HLS that looks like the following:

```
void matrixmul(
  mat_a_t a[MAT_A_ROWS][MAT_A_COLS],
  mat_b_t b[MAT_B_ROWS][MAT_B_COLS],
  result_t res[MAT_A_ROWS][MAT_B_COLS])
{
    #pragma HLS ARRAY_RESHAPE variable=b complete dim=1
    #pragma HLS ARRAY_RESHAPE variable=a complete dim=2
    #pragma HLS INTERFACE ap_fifo port=a
    #pragma HLS INTERFACE ap_fifo port=b
    #pragma HLS INTERFACE ap_fifo port=res
    mat_a_t a_row[MAT_A_ROWS];
    mat_b_t b_copy[MAT_B_ROWS][MAT_B_COLS];
    int tmp = 0;

    // Iterate over the rowa of the A matrix
    Row: for(int i = 0; i < MAT_A_ROWS; i++) {
        // Iterate over the columns of the B matrix
            Col: for(int j = 0; j < MAT_B_COLS; j++) {
            #pragma HLS PIPELINE rewind
            // Do the inner product of a row of A and col of B
            tmp=0;
        // Cache each row (so it's only read once per function)
       if (j == 0)
          Cache_Row: for(int k = 0; k < MAT_A_ROWS; k++)
              a_row[k] = a[i][k];
  
       // Cache all cols (so they are only read once per function)
       if (i == 0)
           Cache_Col: for(int k = 0; k < MAT_B_ROWS; k++)
               b_copy[k][j] = b[k][j];

      Product: for(int k = 0; k < MAT_B_ROWS; k++) {
        tmp += a_row[k] * b_copy[k][j];
      }
  res[i][j] = tmp;
}

```

}  
}

And I import the design into Vivado, which that looks like this:

 ![block](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/5ab133eb2af0b4fd97f4e0c7c0c0844ae0da9e8b.png)

My question is, how do I go about connecting these 2 components? Any help would be appreciated, thank you.

---

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 14, 2020, 6:11pm UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/2 "2020-04-14T18:11:58Z")

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@youn123 if you use axi instead of fifo interfaces it should be easier to connect to the PS.

```
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=a
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=b
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=res 

```

You have to replace with an appropriate valite. The first pragma creates an AXI4-Lite interface to control the module.

You also need to enable the HP ports of the PS.

 ![confPS](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/e33585975904e40405cc074405c59a3568d67733.jpeg)

After that you can `Run Connection Automation` twice and the block design should look like this

 ![bd](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/6102893d20d347f077965f66176afcbd099f84a7.jpeg)

You can also use AXI4-Stream for a,b and res and use other way to move data.

Do you have any preference about how to communicate the IP with the PS?

Mario

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [April 15, 2020, 6:38am UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/3 "2020-04-15T06:38:12Z")

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This example may also be of interest.

> [@How to contribute project to the list of community projects?](https://discuss.pynq.io/t/how-to-contribute-project-to-the-list-of-community-projects/1128):
>
> I would like to contribute an example to the list of community projects. It is maybe a trivial one, but I was not able to find a working example implementing a simple matrix multiplication (on a PYNQ-Z1 board). I thought it might be useful for other members of the community and newbies that come across a similar situation. Link to the project: Best, Medrano

Cathal

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**Author:** ![Sahoora](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sahoora/32/5796_2.png) [@Sahoora](https://discuss.pynq.io/u/Sahoora)\
**Post date:** [April 30, 2024, 6:46am UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/4 "2024-04-30T06:46:48Z")

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Is it possible that in Vivado integrator, we consider a Block Memory Generator for each of a, b, and res which are connected to axi interconnect, and the HLS IP and Zynq can access them through axi interconnect?

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 30, 2024, 9:32am UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/5 "2024-04-30T09:32:00Z")

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Hi @Sahoora,

This post has been resolved. Please open a new issue.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [April 30, 2024, 9:32am UTC](https://discuss.pynq.io/t/how-to-connect-custom-hls-ip-to-zynq-board/1139/6 "2024-04-30T09:32:09Z")

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