# How to design an axi interface IP for pynq

**URL:** <https://discuss.pynq.io/t/how-to-design-an-axi-interface-ip-for-pynq/2218>\
**Category:** Support\
**Created:** [January 7, 2021, 2:10am UTC](https://discuss.pynq.io/t/how-to-design-an-axi-interface-ip-for-pynq/2218 "2021-01-07T02:10:04Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![AllenChenChao](https://avatars.discourse-cdn.com/v4/letter/a/7bcc69/32.png) [@AllenChenChao](https://discuss.pynq.io/u/AllenChenChao)\
**Post date:** [January 7, 2021, 2:10am UTC](https://discuss.pynq.io/t/how-to-design-an-axi-interface-ip-for-pynq/2218/1 "2021-01-07T02:10:05Z")

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Hello, for transfering a list of data from PS to PL, An AXI interface maybe needed.st  
step 1 from ug871,there is a sample on design axi interface IP.

 ![pLV4R04RHx](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3ef5bcbe4e060c419ebf640bd8e0294b6a9a6129.png) ![SumatraPDF_oiQHMRSjUD](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/06dd274e56ef4ce37bbdc4eee7b8206e2621ee43.png) ![SumatraPDF_vx4BR56tnD](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/4/4bb92705bb308fe2195f1aae73f6559f340a8908.png)

step2: could we use xlinl or buffer directly like this tutorial on jupytor:[PYNQ-HelloWorld/resizer\_pl.ipynb at master · Xilinx/PYNQ-HelloWorld · GitHub](https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/pynq_helloworld/notebooks/edge/resizer_pl.ipynb)

 ![chrome_MvRfCcMaj9](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/4/4ea063f0bb93ffee99ba3a1913ca512b628ebceb.png)

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**Author:** ![monkeyboyfr3sh](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/monkeyboyfr3sh/32/1749_2.png) [@monkeyboyfr3sh](https://discuss.pynq.io/u/monkeyboyfr3sh)\
**Post date:** [January 7, 2021, 5:46pm UTC](https://discuss.pynq.io/t/how-to-design-an-axi-interface-ip-for-pynq/2218/2 "2021-01-07T17:46:35Z")

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Hi, I’m just a fellow Pynq user so I won’t have all the answers but recently I spent a bit of time figuring out how to set this up.

First, I recommend giving this a read: [Understanding AXI Addressing](https://zipcpu.com/blog/2019/04/27/axi-addr.html)  
It goes over normal AXI transactions and what you should expect your waveforms to look like.

If that makes sense to you then from there I recommend this video as for how to actually setup an AXI interface in Vivado: [Generating custom AXI4-Stream IP core using Xilinx Vivado - YouTube](https://youtu.be/chs5mdwMchQ?t=1879)

Hopefully this helps. I know this stuff can be a bit convoluted to figure out from scratch so good luck!