# How to use axi interface created by HLS correctly?

**URL:** <https://discuss.pynq.io/t/how-to-use-axi-interface-created-by-hls-correctly/2237>\
**Category:** Support\
**Created:** [January 13, 2021, 9:53am UTC](https://discuss.pynq.io/t/how-to-use-axi-interface-created-by-hls-correctly/2237 "2021-01-13T09:53:54Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![AllenChenChao](https://avatars.discourse-cdn.com/v4/letter/a/7bcc69/32.png) [@AllenChenChao](https://discuss.pynq.io/u/AllenChenChao)\
**Post date:** [January 13, 2021, 9:53am UTC](https://discuss.pynq.io/t/how-to-use-axi-interface-created-by-hls-correctly/2237/1 "2021-01-13T09:53:54Z")

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Hello, I want to use axi interface in PYNQ.So I created an axi master IP with HLS examle project.  
I use that IP on vivado, and I find I can’t **Creat HDL wrapper** , there is an error: **[BD 41-758] The following clock pins are not connected to a valid clock source: /processing\_system7\_0/M\_AXI\_GP0\_ACLK**  
I don’t how to deal with it. I choose or not choose HP0 or GP0, It does’t work.  
Is anyone know how to deal with it? I want to test it n PYNQ, hope it could be successfully.

 ![vivado_kHFT7twXZP](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fdc229086199c3f900a29ec852cf8be5bc244059.png)

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [January 17, 2021, 7:51pm UTC](https://discuss.pynq.io/t/how-to-use-axi-interface-created-by-hls-correctly/2237/2 "2021-01-17T19:51:40Z")

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@AllenChenChao,

The pin `M_AXI_GP0_ACLK` in the ZYNQ7 PS is disconnected, you either connect the pin to a clock or disable the GP0

Mario