# How to use the DMA

**URL:** <https://discuss.pynq.io/t/how-to-use-the-dma/3797>\
**Category:** Support\
**Created:** [March 7, 2022, 6:23pm UTC](https://discuss.pynq.io/t/how-to-use-the-dma/3797 "2022-03-07T18:23:48Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![savannah](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/savannah/32/3182_2.png) [@savannah](https://discuss.pynq.io/u/savannah)\
**Post date:** [March 7, 2022, 6:23pm UTC](https://discuss.pynq.io/t/how-to-use-the-dma/3797/1 "2022-03-07T18:23:48Z")

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[admin edit: moved to new post]

Thank you so much. I included the .hwh file, and now I am able to load the overlay properly. However, I am having trouble figuring out how to read/write to the FPGA memory and perform the vector addition. I have tried the following Python code which I have modified from the code in this [discussion board](https://discuss.pynq.io/t/vector-addition-correct-output-only-on-every-other-elements/3073); however, the code gets stuck in the while loop and never completes.

```auto
import numpy as np 
vec_x = np.array([1, 2, 3, 4, 5, 6, 7, 8])
vec_y = np.array([10, 10, 10, 10, 10, 10, 10, 10])
vec_z = np.array([0, 0, 0, 0, 0, 0, 0, 0])

from pynq import Overlay
# Load the overlay
overlay = Overlay('/home/xilinx/pynq/overlays/vector_add/vecAdder.bit')
# IP alias
vecAdd=overlay.vector_add 

# Allocate contiguous buffer for memory transfer
x_buffer = allocate(shape=(N,), dtype=np.int)
y_buffer = allocate(shape=(N,), dtype=np.int)
z_buffer = allocate(shape=(N,), dtype=np.int)
# Copy the DNA string to the in_buffer
np.copyto(x_buffer,vec_x)
np.copyto(y_buffer,vec_y)
np.copyto(z_buffer,vec_z)

# initialize AXI with address and length, 
vecAdd.write(0x10,z_buffer.physical_address) # vector Z is AXI so need to initialize address
vecAdd.write(0x18,y_buffer.physical_address) # vector Y is AXI so need to initialize address
vecAdd.write(0x20,x_buffer.physical_address) # vector X is AXI so need to initialize address
vecAdd.write(0x28,N) # initialize N
vecAdd.write(0x00,0x01) # start

while vecAdd.read(0x00 & 0x4)!= 0x04:
    pass

vecAdd.write(0x00,0x00) # stop   
np.copyto(vec_z, z_buffer)

```

Should I be using DMA to do the reading/writing? Like I mentioned previously. This all is very new to me and I am trying to learn as much as I can. Any advice on how to fix this would be greatly appreciated! Thanks!

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [March 8, 2022, 8:29am UTC](https://discuss.pynq.io/t/how-to-use-the-dma/3797/2 "2022-03-08T08:29:43Z")

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Hi,

If you mark a reply as solution, please open a new post for future questions. The second question is not related to the first one, hence it will not help other people.

There are detailed tutorials on the use of DMA and DMA + HLS IP. I suggest you have a look, these should answer your questions.

> [@Tutorial: PYNQ DMA (Part 1: Hardware design)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133):
>
> PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

> [@Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344):
>
> Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design) In a [previous tutorial](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133) I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, [part 2](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-tutorial-part-2-vivado-design/3345) shows how to build the Vivad…

Mario