# How to write data on hp0 fpd port

**URL:** <https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403>\
**Category:** Support\
**Created:** [June 30, 2022, 7:49am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403 "2022-06-30T07:49:13Z")\
**Posts on this page:** 20\
**Page:** 1

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 7:49am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/1 "2022-06-30T07:49:13Z")

</div>

\<Pynq 2.6, ZCU104, Vivado 2020.1\>  
I am trying to use memory mapped interface of axi video mixer to transfer the overlay picture. How to write the image data through hp0 port.  
Could this code work?

```auto
from pynq import MMIO
base_input_address=0x7F00_0000
PL = MMIO(base_input_address, 100000)
input_registers = PL.array[(base_input_address//4):(base_input_address//4)+3*64*64]
input_registers[:] = logo.ravel()

```

![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fcdf4e427603dab7783793ffe31b7eabe2de1bc5.png)

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/800f196985c467676ba85c5896c4b10c0c85319e.png)

Thanks,  
Mizan

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 8:00am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/2 "2022-06-30T08:00:15Z")

</div>

Hi @mizan,

Cathal wrote a tutorial showing how to use the AXI4 master interfaces with a HLS IP

> [@Tutorial: AXI Master interfaces with HLS IP](https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032):
>
> PYNQ HLS AXI Master tutorial Introduction Previous tutorials show how to build IP with AXI stream interfaces and how they can be connected in a Vivado project to an AXI DMA. The DMA can be controlled from PYNQ to send data to the IP and receive results. AXI stream interfaces are useful if you are connecting multiple IP together in a dataflow type architecture. However, you don’t have to use AXI streams and DMAs with HLS IP. HLS supports AXI master interfaces which can read and write data as r…

I don’t think your code will work, because the AXI4 interface you want to use should initiate the transfers.

Mario

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 8:24am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/3 "2022-06-30T08:24:13Z")

</div>

My first actual try was setting the address register value through axi lite interface and transferring the image. It is not working. That’s why I wanted to try previously stated code.

```auto
logo = allocate(shape=(64, 64, 3), dtype=np.uint8, cacheable=True)
logo[:]= cv2.imread('flip.png')
vmixer.write(0x240,logo.physical_address)

```

But it doesn’t have any impact, the image is not transferring (not showing on overlay)

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 8:42am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/4 "2022-06-30T08:42:51Z")

</div>

Did you start the IP?

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 8:44am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/5 "2022-06-30T08:44:25Z")

</div>

yes, the Ip is working fine. I can see the overlay region as well on image.

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 8:46am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/6 "2022-06-30T08:46:35Z")

</div>

I also notice that the IP only has access to 16MB of the DDR memory. You should change this, so the IP can access the full DDR range.

It is likely that the `logo.physical_address` it is outside of the range that the IP can access.

Mario

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 8:48am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/7 "2022-06-30T08:48:42Z")

</div>

Actually, it was on full 2g when I have tried the first code. for later code, i have changed it. I will try again.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 8:50am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/8 "2022-06-30T08:50:13Z")

</div>

Go for the 4GB. Also check the value of `logo.physical_address` to see if it is within range.

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 8:53am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/9 "2022-06-30T08:53:54Z")

</div>

2G is full ddr for zcu104. I have updated the bitstream and tried. Still same output. No image.  
Just to show the example image.  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/ca226cf46f2d024c22fda60f1dad7beecc6908fb.png)

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 8:55am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/10 "2022-06-30T08:55:15Z")

</div>

Just to make sure, i am trying this code:

> [@mizan](#):
>
> ```auto
> logo = allocate(shape=(64, 64, 3), dtype=np.uint8, cacheable=True)
> logo[:]= cv2.imread('flip.png')
> vmixer.write(0x240,logo.physical_address)
> 
> ```

My current project has 8 overlays and the project is working fine with 8 vdma which output streams go to the video mixer. But I don’t want to add so much code and vdmas for the project. That’s why I wanted to switch to memory-mapped interface. If there is any other way it could be done, it would be helpful to know.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 9:07am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/11 "2022-06-30T09:07:44Z")

</div>

No, this is the only way it can be done. You need to pass the pointer to memory and then start the IP.

What value are you getting for `logo.physical_address`?

I would also suggest you try to reproduce Cathal’s tutorial. Your IP seems to be more complex as it has streams as well. Once you have establish that this methodology works in your board, you can start debugging your IP.

Other things to consider, is 0x240 the address of the pointer? How does your register\_map look like?

Mario

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 9:13am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/12 "2022-06-30T09:13:22Z")

</div>

It is not my ip. This video mixer IP from xilinx. At register 0x240 is memory-mapped address for layer 1 overlay according to the product guide.

> [@marioruiz](#):
>
> I would also suggest you try to reproduce Cathal’s tutorial. Your IP seems to be more complex as it has streams as well. Once you have establish that this methodology works in your board, you can start debugging your IP.

That might work for hls IP, but i needed it for this IP. The process he applied i already have it in the project. To put the address, and change data according in the buffer later on. If there is other changes i would have tried.

> What value are you getting for logo.physical\_address?

It shows an address and I can read the image as well from that address. (5FC84000). It is different every run.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 9:23am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/13 "2022-06-30T09:23:11Z")

</div>

Hi,

> It shows an address and I can read the image as well from that address. (5FC84000). It is different every run.

Yes, this is expected.

Are you enabling the layer in the Layer Enable (0x0040) Register?  
[https://docs.xilinx.com/r/en-US/pg243-v-mix/Layer-Enable-0x0040-Register](https://docs.xilinx.com/r/en-US/pg243-v-mix/Layer-Enable-0x0040-Register)

I haven’t used this IP before. You may need to review the documentation carefully and write the appropriate value to the necessary registers

[https://docs.xilinx.com/r/en-US/pg243-v-mix/Layer-Registers](https://docs.xilinx.com/r/en-US/pg243-v-mix/Layer-Registers)

Mario

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 9:27am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/14 "2022-06-30T09:27:14Z")

</div>

I am using it for quite a long time now, but have not used the memory-mapped interface. Yes, I enabled the overlay that’s why the overlay is seen in the picture. I am using this IP, for multiple layers for other projects and the settings are okay, I am quite sure about it. There is not much complexity in the register value for this IP. For memory mapped there is only two registers are responsible, where i am using the first one only as i am using RGB image.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 10:16am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/15 "2022-06-30T10:16:46Z")

</div>

Can you please share how the IP is configured?

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 10:40am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/16 "2022-06-30T10:40:12Z")

</div>

i share the complete code here:

```auto
from pynq import Overlay, allocate
from pynq.lib.video import VideoMode
import cv2
from matplotlib import pyplot as plt
import time
import numpy as np
overlay = Overlay('/home/xilinx/jupyter_notebooks/v_mix_mm.bit')
test_image = allocate(shape=(1080, 1920, 3), dtype=np.uint8, cacheable=True)
logo = allocate(shape=(64, 64, 3), dtype=np.uint8, cacheable=True)

test_image[:]= cv2.imread('test.bmp')

frameMode=VideoMode(1920, 1080, 24)
vdma = overlay.axi_vdma_0
vdma.readchannel.mode= frameMode
vdma.writechannel.mode= frameMode

vdma.readchannel.start()
vdma.writechannel.start()

time.sleep(0.1)
vmixer= overlay.v_mix_0
vmixer.write(0x10,0x780)
vmixer.write(0x18,0x438)
vmixer.write(0x40,0x03)
vmixer.write(0x100,0xFF)
vmixer.write(0x118,0x780)
vmixer.write(0x128,0x438)
vmixer.write(0x200,220)
vmixer.write(0x208,100)
vmixer.write(0x210,200)
vmixer.write(0x218,64)
vmixer.write(0x228,64)
logo = allocate(shape=(64,64,3), dtype=np.uint8)
logo[:]= cv2.imread('flip.png')
vmixer.write(0x240,logo.physical_address)
vmixer.write(0x0,0x81)
time.sleep(0.5)
for i in range(10):
    vdma.writechannel.writeframe(test_image)
    frame2 = vdma.readchannel.readframe()
plt.imshow(frame2)

```

the vivado design only consists of videomixer, vdma, interrupt controller ip.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 10:42am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/17 "2022-06-30T10:42:51Z")

</div>

Can you provide a screenshot of the IP configuration in Vivado?

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 10:45am UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/18 "2022-06-30T10:45:38Z")

</div>

![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/9/9cc46f1584051271669140f36870372803683e9a.png)  
You mean for video mixer only? or others also?

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 30, 2022, 1:02pm UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/19 "2022-06-30T13:02:08Z")

</div>

Video mixer only

---

<div class="post-metadata">

**Author:** ![mizan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mizan/32/2119_2.png) [@mizan](https://discuss.pynq.io/u/mizan)\
**Post date:** [June 30, 2022, 1:02pm UTC](https://discuss.pynq.io/t/how-to-write-data-on-hp0-fpd-port/4403/20 "2022-06-30T13:02:48Z")

</div>

given then 😉

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