# Image Processing Acceleration **URL:** \ **Category:** Support\ **Created:** [October 28, 2020, 8:07pm UTC](https://discuss.pynq.io/t/image-processing-acceleration/1955 "2020-10-28T20:07:45Z")\ **Posts on this page:** 1\ **Showing post:** 5
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [October 29, 2020, 5:48pm UTC](https://discuss.pynq.io/t/image-processing-acceleration/1955/5 "2020-10-29T17:48:53Z")
The AXI interface is the default interface type used in Vivado. One way to do this would be to add an AXI interface to your design. An AXI stream for your pixels would be the most straightforward. You can then stream data to your IP using a DMA. You could also build an AXI master interface where your IP could access DRAM directly (without needing a DMA). This interface is more complicated though. For any of the AXI interfaces, I would recommend you use a Wizard in Vivado to generate the HDL for the AXI interface(s) you want. I posted in another topic about this recently: > [@Axis stream off by one](https://discuss.pynq.io/t/axis-stream-off-by-one/1818/6): > > I’m not sure about standard testbenches, but the testbenches are usually easier to write. You didn’t ask this, but it may help; I’d never write my own AXI interface logic as I think you did in this example. You can generate a HDL (VHDL/Verilog) AXI interface template in Vivado, and add your HDL for the logic. I’d always use this if I needed a HDL AXI interface. Create and Package IP wizard If you use HLS, it will generate the AXI interfaces automatically. There are AXI protocol… Once you generate the template, you can integrate your Verilog into the generated code. Cathal --- _[View the full topic](https://discuss.pynq.io/t/image-processing-acceleration/1955)._