# Instantiate and control a microblaze IOP

**URL:** <https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478>\
**Category:** Support\
**Created:** [March 26, 2021, 4:20pm UTC](https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478 "2021-03-26T16:20:55Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![lucDu93](https://avatars.discourse-cdn.com/v4/letter/l/91b2a8/32.png) [@lucDu93](https://discuss.pynq.io/u/lucDu93)\
**Post date:** [March 26, 2021, 4:20pm UTC](https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478/1 "2021-03-26T16:20:55Z")

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Hi,  
I would like to get some help in the process of adding a microblaze IOP in my current hardware design (which consists of a zynq and a custom IP) and use this IOP to control a PMOD in my pynq-Z2 board throught a jupyter notebook. The Doc is a bit blur for me ([MicroBlaze Subsystem — Python productivity for Zynq (Pynq)](https://pynq.readthedocs.io/en/latest/pynq_libraries/pynq_microblaze_subsystem.html?highlight=iop)).  
Best regard,  
Luc Forestier.

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [March 27, 2021, 11:50am UTC](https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478/2 "2021-03-27T11:50:55Z")

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Hi @lucDu93,

I would suggest to start with the base overlay and:

1. remove the hardware you do not need from it
2. Add your custom IP

> **[PYNQ/boards/Pynq-Z2/base at master · Xilinx/PYNQ](https://github.com/Xilinx/PYNQ/tree/master/boards/Pynq-Z2/base)**
>
> master/boards/Pynq-Z2/base

Mario

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<div class="post-metadata">

**Author:** ![lucDu93](https://avatars.discourse-cdn.com/v4/letter/l/91b2a8/32.png) [@lucDu93](https://discuss.pynq.io/u/lucDu93)\
**Post date:** [March 27, 2021, 12:53pm UTC](https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478/3 "2021-03-27T12:53:54Z")

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Thank you for the reply Mario. I thought of that solution at the beginning but I found that the base hardware design is too complicated (I don’t know what to remove, also I’ve found that the pmoda is mixed with rpi outputs on pynq-z2). I will be very happy if someone could make a tutorial about it. (I’m working with Vivado 2018.2 and image v2.3).[base.pdf](https://discuss.pynq.io/uploads/short-url/qAY6jWXFuKncN9cDABr8qyBliBy.pdf) (217.3 KB)

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<div class="post-metadata">

**Author:** ![lucDu93](https://avatars.discourse-cdn.com/v4/letter/l/91b2a8/32.png) [@lucDu93](https://discuss.pynq.io/u/lucDu93)\
**Post date:** [March 28, 2021, 8:14am UTC](https://discuss.pynq.io/t/instantiate-and-control-a-microblaze-iop/2478/4 "2021-03-28T08:14:48Z")

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Hi,  
I have created the hardware part of what I wanted (instantiating a microblaze IOP in my design) by following this tutorial : [PYNQ and IOP on Ultra96 Breakout - Hackster.io](https://www.hackster.io/adam-taylor/pynq-and-iop-on-ultra96-breakout-84564c) (till the ‘Using the IOP’ section), here is the design [design\_1.pdf](https://discuss.pynq.io/uploads/short-url/dRpPSo53BgSJ47kb2OjRv4ZAdSg.pdf) (75.3 KB) and addressing table, and the bitstream was generated correctly. Then I followed the doc ([MicroBlaze Subsystem — Python productivity for Zynq (Pynq) v1.0](https://pynq.readthedocs.io/en/v2.3/pynq_libraries/pynq_microblaze_subsystem.html?highlight=subsystem#creating-a-new-pynq-microblaze)) and exported the bsp folder with .bit .hwh and .tcl files of my design. I opened them on jupyter, loaded the bitstream and added the bsp folder, but when I use the microblaze (%%microblaze overlay.pmod1) to perform a simple addition function, I get this message : '“Compile FAILED Binary file too big for IP”. Can someone help me, please ?

 ![Screenshot from 2021-03-28 09-44-49](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/6/643ffbebd35d5e4c20e50e6e1f286b3da3274427.png)