# Intefarcing of custom IP having HLS stream of ap\_uint

**URL:** <https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980>\
**Category:** Support\
**Created:** [November 30, 2022, 4:42pm UTC](https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980 "2022-11-30T16:42:37Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![Sheikh\_Talha](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sheikh_talha/32/4084_2.png) [@Sheikh\_Talha](https://discuss.pynq.io/u/Sheikh_Talha)\
**Post date:** [November 30, 2022, 4:42pm UTC](https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980/1 "2022-11-30T16:42:37Z")

</div>

Hello I am trying to implement convolution through finn hlss library. I am facing issues while creating the interface for Vivado. I can not connect it to DMA.

My top function looks like this:  
#include “edgedetection.h”  
#include \<hls\_stream.h\>  
using namespace hls;  
#include “convlayer.h”

#define IFC IFM\_Channels1  
#define OFC OFM\_Channels1

typedef stream\<ap\_uint\<IFC \* INPUT\_PRECISION\>\> dataInS;  
typedef stream\<ap\_uint\<OFC \* ACTIVATION\_PRECISION\>\> dataOutS;

void ConvLayer\_B\_custom(dataInS &in, dataOutS &out, int const numReps) {  
#pragma HLS INTERFACE s\_axilite port=return bundle=control  
#pragma HLS INTERFACE s\_axilite port=numReps bundle=control  
#pragma HLS INTERFACE axis port=&in bundle=hostmem  
#pragma HLS INTERFACE axis port=&out bundle=hostmem  
#pragma HLS DATAFLOW  
static FixedPointWeights\<SIMD,ap\_uint\<32\>,PE,TILES\> weights= {  
-1,-2,-1,  
0, 0, 0,  
1, 2, 1  
};

ConvLayer\_Batch\<K, IFC, IFD, OFC, OFD, SIMD, PE, Slice\<ap\_int\<INPUT\_PRECISION\> \>, Slice\<ap\_int \>, Identity\>(  
in, out, weights, PassThroughActivation\<ap\_int\>(), numReps, ap\_resource\_dsp());

}

My vivado block design looks like this:

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c726c16f2de665062c15165d5ad76aad01c45999.png)

I can not connect my input and output port to DMA.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [December 1, 2022, 9:22am UTC](https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980/2 "2022-12-01T09:22:32Z")

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Hi @Sheikh_Talha,

Welcome to the PYNQ community.

Why are you bundling both AXI4-Stream interfaces to the same name? Each of the should have their own name.

Mario

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<div class="post-metadata">

**Author:** ![Sheikh\_Talha](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sheikh_talha/32/4084_2.png) [@Sheikh\_Talha](https://discuss.pynq.io/u/Sheikh_Talha)\
**Post date:** [December 2, 2022, 7:02pm UTC](https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980/3 "2022-12-02T19:02:18Z")

</div>

Even when I make those changes like this:

typedef stream\<ap\_uint\<IFC \* INPUT\_PRECISION\>\> dataInS;  
typedef stream\<ap\_uint\<OFC \* ACTIVATION\_PRECISION\>\> dataOutS;

void ConvLayer\_B\_custom(dataInS &in, dataOutS &out, int const numReps) {  
#pragma HLS INTERFACE s\_axilite port=return bundle=control  
#pragma HLS INTERFACE s\_axilite port=numReps bundle=control  
#pragma HLS INTERFACE axis port=&in bundle=in\_hostmem  
#pragma HLS INTERFACE axis port=&out bundle=out\_hostmem  
#pragma HLS DATAFLOW

static FixedPointWeights\<SIMD,ap\_uint\<32\>,PE,TILES\> weights= {  
-1,-2,-1,  
0, 0, 0,  
1, 2, 1  
};

ConvLayer\_Batch\<K, IFC, IFD, OFC, OFD, SIMD, PE, Slice\<ap\_int\<INPUT\_PRECISION\> \>, Slice\<ap\_int \>, Identity\>(  
in, out, weights, PassThroughActivation\<ap\_int\>(), numReps, ap\_resource\_dsp());

}

I am still getting the same type of ports when i import my ip to vivado block design.

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [December 2, 2022, 8:22pm UTC](https://discuss.pynq.io/t/intefarcing-of-custom-ip-having-hls-stream-of-ap-uint/4980/4 "2022-12-02T20:22:49Z")

</div>

You shouldn’t be using &in and &out in the directives. The pragma for the AXI4-Stream interfaces should be

```nohighlight
#pragma HLS INTERFACE axis port=in bundle=in_hostmem
#pragma HLS INTERFACE axis port=out bundle=out_hostmem

```

If after this change, you are still facing issues. I suggest you ask the question in the FINN or Xilinx forums.

Mario