# Latency in DRAM-RF data converter path

**URL:** <https://discuss.pynq.io/t/latency-in-dram-rf-data-converter-path/8217>\
**Category:** Support\
**Created:** [March 26, 2025, 4:10pm UTC](https://discuss.pynq.io/t/latency-in-dram-rf-data-converter-path/8217 "2025-03-26T16:10:52Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Hasitha](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hasitha/32/6780_2.png) [@Hasitha](https://discuss.pynq.io/u/Hasitha)\
**Post date:** [March 26, 2025, 4:10pm UTC](https://discuss.pynq.io/t/latency-in-dram-rf-data-converter-path/8217/1 "2025-03-26T16:10:52Z")

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I am using Pynq 3.0 on a ZCU 111 board. I am trying to pass data from the DRAM continuously to the DAC(RF data converter) through a DMA. At the same time, I want to receive the transmitted signal through a wired channel which is connected to the ADC.I have the following problems

-Since the DMA transfer is software triggered, can we have a continuous stream from DRAM to the data converter?(There should not be any delay in passing samples in the rf data converter)  
-If it is not possible, do I need to save chunks of data to a BRAM, then pass it to the data converter?  
-I have two streams from the ADC for I and Q signals. I have connected two DMAs for each channel. When I trigger the transfer, they do not start simultaneously, causing the saved I and Q samples in memory to be misaligned. How can I ensure they are synchronized?