I want to use M.2 NVMe SSD(M-key) with FPGA using PCIe.
I’ve few questions, I would appreciate your answers.
NVMe SSD are accept refclock of 100MHz, HCSL Standard, Does FPGA(PL-GTY) should also be provided HCSL 100MHz REF Clock or It could be of any standard(LVDS/LVPECL)?
I presume these reference clock to the PCIe SSD and FPGA should be synchronous. RIght?
How should the reset signal of M.2 SSD be driven? Can it be from Host?
Any timing diagram to be carried out, i.e. First SSD Should be up and then processor?
Since SSD is end point (slave) in PCIe structure and Processor(/FPGA) is Root complex (Master)
So, during Enumeration from Processor, Slave should be out of reset for enumeration to get complete successfully
So how can Processor drive reset to SSD won’t it be contradiction?