# Mismatch of PYNQ Data Stream from DMA on Ultrascale+ **URL:** \ **Category:** Support\ **Created:** [September 14, 2024, 4:20pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490 "2024-09-14T16:20:41Z")\ **Posts on this page:** 11\ **Page:** 1
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 14, 2024, 4:20pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/1 "2024-09-14T16:20:41Z")
-PYNQ Version 3.0.1 -Board: Ultra 96 -Vivado & VITIS HLS 2022.0.2 I tried to imitate this tutorial [Tutorial: using a HLS stream IP with DMA (Part 3: Using the HLS IP from PYNQ)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-3-using-the-hls-ip-from-pynq/3346) on Ultrascale+. The results are all 0 when I run PYNQ script. I used both HP0, HP2 for Ultrascale + and set them to 64 bits. This is my axi dma config: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/6/6996b7bafd8e9ca919d88b761b2e1c69bb8eb55b.png) Can anyone help me with this? ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 14, 2024, 6:45pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/2 "2024-09-14T18:45:54Z")
Hi, Which script are you running on the board? Is it a python code? ---
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 15, 2024, 12:45am UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/3 "2024-09-15T00:45:16Z")
Hi Matthew, this is my python script: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/f1fa9574276a3a0e5dbbc59cba2219dac70414eb.png) I also had incorrect output when running this tutorial [Tutorial: PYNQ DMA (Part 1: Hardware design)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133) also I got it correct in the first time. Is it because of some cache problems with PYNQ? ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 15, 2024, 5:11am UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/4 "2024-09-15T05:11:20Z")
**also I got it correct in the first time. Is it because of some cache problems with PYNQ?** Do you still have a problem with the DMA block? If yes, which error is displayed? Or is the python code freezing during the data transfer? **The results are all 0 when I run PYNQ script.** So your problem is that the line : _for i in range(10):_ _print(‘0x’ + format(output\_buffer[i], ‘02x’))_ Is displaying only ten 0 in hexadecimal, so ten 0x00? Am I understanding correctly? ---
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 15, 2024, 5:57am UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/5 "2024-09-15T05:57:06Z")
**Do you still have a problem with the DMA block? If yes, which error is displayed? Or is the python code freezing during the data transfer?** There are no frozen or errors, this is my result: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/168cd8ba61e0c8ffff5b3f6bed4622da182285a5.jpeg) The setting is still the same as my first post. **Is displaying only ten 0 in hexadecimal, so ten 0x00? Am I understanding correctly?** Yes, its correct. ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 15, 2024, 2:38pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/6 "2024-09-15T14:38:20Z")
Can you please send the **dma.py** code? I am sorry, I did not understand your issue. It is normal that the DMA, the output is empty before the transfer as DMA is empty when initialized. Then it is filled after the transfer. Is your problem the fact that the values in the DMA after the transfer are not corresponding to your inputs? ---
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 15, 2024, 2:53pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/7 "2024-09-15T14:53:34Z")
Hi, I got the correct results for both tutorials but I only used HP0 port and then let the auto connection do the rest. My dma.py is exactly the same as this tutorial [Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-2-using-the-dma-from-pynq/3134). ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 15, 2024, 2:58pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/8 "2024-09-15T14:58:44Z")
So what is your problem? Do you want to use a port different than the HP0 port? Is it normal that your output after transfer is different than your input? They should be the same like in ([Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-2-using-the-dma-from-pynq/3134)) ---
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 15, 2024, 3:11pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/9 "2024-09-15T15:11:32Z")
Because using two ports does not work, so I just switched to 1 port to move on with my school project. I still don’t know why two ports do not work in my case. ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [September 15, 2024, 3:55pm UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/10 "2024-09-15T15:55:18Z")
As your architecture is working with 1 port HP0, do you still need assistance? Or do you want to close this request? ---
**Author:** ![Th\_ng\_Nguy\_n\_D\_c](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/th_ng_nguy_n_d_c/32/6294_2.png) [@Th\_ng\_Nguy\_n\_D\_c](https://discuss.pynq.io/u/Th_ng_Nguy_n_D_c)\ **Post date:** [September 16, 2024, 2:58am UTC](https://discuss.pynq.io/t/mismatch-of-pynq-data-stream-from-dma-on-ultrascale/7490/11 "2024-09-16T02:58:01Z")
Yes, we can close this.