# On board SFP with ZCU111 and PYNQ

**URL:** <https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757>\
**Category:** Support\
**Created:** [November 20, 2024, 5:42pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757 "2024-11-20T17:42:08Z")\
**Posts on this page:** 9\
**Page:** 1

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [November 20, 2024, 5:42pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/1 "2024-11-20T17:42:08Z")

</div>

Hi folks,  
this is my setup:

```
- Ubuntu 18.04 in Virtual Box
- Petalinux 2022.1
- Vivado 2022.1
- Repository for RFSoC-PYNQ V3.0
- Xilinx ZCU111 board

```

I’would like to recreate this Xilinx project ([PL eth 1G](https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet/tree/main/2019.2/pl_eth_1g)) but it’s not clear to me if it possible the same implementation under PYNQ.

Up to now i’m able to generate the embedded board image from Vivado project under petalinux, in this case after the boot i have booth ethernet link eth0 and eth1 up and running, where eth1 is the SFP0 on board with the optical transceiver module 1000base X.

If i try the same think with the repository of the source code and build scripts for the RFSoC-PYNQ from [GitHub RFsoc](https://github.com/Xilinx/RFSoC-PYNQ), with the same Vivado hardware project used before the second ethernet link eth1 is not visible:

 ![pynq_boot](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/cf33194662d94d4fd738b8d5c8c75bd1de960d1b.png)

 ![pynq_boot2](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/1892218577515e0f9ae442d7501093679cc3cf39.png)

I’m not really a Petalinux expert, please can someone help me understand where i’m going wrong?

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [November 21, 2024, 11:33am UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/2 "2024-11-21T11:33:41Z")

</div>

Hi @Federico,

Have you modified the device tree accordingly to include this?

Mario

---

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [November 22, 2024, 4:43pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/3 "2024-11-22T16:43:45Z")

</div>

Hi @marioruiz ,  
thanks for replying. Honestly i have a lot of confusion about the device tree.

This is the last version of my DT, i used the DT generator from .xsa file:

> /include/ “system-conf.dtsi”  
> / {  
> amba\_pl@0 {  
> data\_source\_top0:data\_source\_top@a0000000 {  
> compatible = “xlnx,data-source-top-1.0”;  
> reg = \<0x0 0xa0000000 0x0 0x10000\>;  
> };  
> };  
> };
> 
> &i2c1 {  
> i2c-mux@74 { /\* u26 _/  
> i2c@5 {  
> #address-cells = \<1\>;  
> #size-cells = \<0\>;  
> reg = \<5\>;  
> sc18is603@2f { /_ sc18is602 - u93 _/  
> /_ Part name is sc18is602 - using sc18is603 to match ZCU111 system-user.dtsi \*/  
> compatible = “nxp,sc18is602b”;  
> reg = \<0x2f\>;  
> #address-cells = \<0x1\>;  
> #size-cells = \<0x0\>;  
> lmxC@0 {  
> compatible = “ti,lmx2594”;  
> reg = \<0x0\>;  
> spi-max-frequency = \<400000\>;  
> num\_bytes = \<4\>;  
> };  
> lmk@1 {  
> compatible = “ti,lmk04208”;  
> reg = \<0x1\>;  
> spi-max-frequency = \<400000\>;  
> num\_bytes = \<4\>;  
> };  
> lmxB@2 {  
> compatible = “ti,lmx2594”;  
> reg = \<0x2\>;  
> spi-max-frequency = \<400000\>;  
> num\_bytes = \<4\>;  
> };  
> lmxA@3 {  
> compatible = “ti,lmx2594”;  
> reg = \<0x3\>;  
> spi-max-frequency = \<400000\>;  
> num\_bytes = \<4\>;  
> };  
> };  
> };  
> };  
> };
> 
> axi\_dma\_0: dma@a0000000 {  
> #dma-cells = \<1\>;  
> clock-names = “s\_axi\_lite\_aclk”, “m\_axi\_sg\_aclk”, “m\_axi\_mm2s\_aclk”, “m\_axi\_s2mm\_aclk”;  
> clocks = \<&zynqmp\_clk 71\>, \<&zynqmp\_clk 71\>, \<&zynqmp\_clk 71\>, \<&zynqmp\_clk 71\>;  
> compatible = “xlnx,eth-dma”;  
> interrupt-names = “mm2s\_introut”, “s2mm\_introut”;  
> interrupt-parent = \<&gic\>;  
> interrupts = \<0 89 4 0 90 4\>;  
> reg = \<0x0 0xa0000000 0x0 0x10000\>;  
> xlnx,addrwidth = /bits/ 8 \<0x20\>;  
> xlnx,include-dre ;  
> xlnx,num-queues = /bits/ 16 \<0x1\>;  
> };  
> axi\_ethernet\_0: ethernet@a0040000 {  
> axistream-connected = \<&axi\_dma\_0\>;  
> axistream-control-connected = \<&axi\_dma\_0\>;  
> clock-frequency = \<100000000\>;  
> clock-names = “s\_axi\_lite\_clk”, “axis\_clk”, “ref\_clk”;  
> clocks = \<&zynqmp\_clk 71\>, \<&zynqmp\_clk 71\>, \<&zynqmp\_clk 72\>;  
> compatible = “xlnx,axi-ethernet-7.2”, “xlnx,axi-ethernet-1.00.a”;  
> device\_type = “network”;  
> interrupt-names = “interrupt”, “mm2s\_introut”, “s2mm\_introut”;  
> interrupt-parent = \<&gic\>;  
> interrupts = \<0 91 4 0 89 4 0 90 4\>;  
> local-mac-address = [00 0a 35 00 00 00];  
> phy-handle = \<&axi\_ethernet\_0phy2\>;  
> phy-mode = “1000base-x”;  
> reg = \<0x0 0xa0040000 0x0 0x40000\>;  
> xlnx = \<0x0\>;  
> xlnx,axiliteclkrate = \<0x0\>;  
> xlnx,axisclkrate = \<0x0\>;  
> xlnx,channel-ids = \<0x1\>;  
> xlnx,clockselection = \<0x0\>;  
> xlnx,enableasyncsgmii = \<0x0\>;  
> xlnx,gt-type = \<0x0\>;  
> xlnx,gtinex = \<0x0\>;  
> xlnx,gtlocation = \<0x0\>;  
> xlnx,gtrefclksrc = \<0x0\>;  
> xlnx,include-dre ;  
> xlnx,instantiatebitslice0 = \<0x0\>;  
> xlnx,num-queues = /bits/ 16 \<0x1\>;  
> xlnx,phy-type = \<0x5\>;  
> xlnx,phyaddr = \<0x2\>;  
> xlnx,phyrst-board-interface-dummy-port = \<0x0\>;  
> xlnx,rable = \<0x0\>;  
> xlnx,rxcsum = \<0x2\>;  
> xlnx,rxlane0-placement = \<0x0\>;  
> xlnx,rxlane1-placement = \<0x0\>;  
> xlnx,rxmem = \<0x8000\>;  
> xlnx,rxnibblebitslice0used = \<0x0\>;  
> xlnx,tx-in-upper-nibble = \<0x1\>;  
> xlnx,txcsum = \<0x2\>;  
> xlnx,txlane0-placement = \<0x0\>;  
> xlnx,txlane1-placement = \<0x0\>;  
> xlnx,versal-gt-board-flow = \<0x0\>;  
> zclock-names = “NULL”;  
> zclocks = “NULL”;  
> axi\_ethernet\_0\_mdio: mdio {  
> #address-cells = \<1\>;  
> #size-cells = \<0\>;  
> axi\_ethernet\_0phy2: phy@2 {  
> device\_type = “ethernet-phy”;  
> reg = \<2\>;  
> };  
> };  
> };

Federico

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [November 22, 2024, 6:35pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/4 "2024-11-22T18:35:51Z")

</div>

Did you include these changes as part of the user device tree?

> **[RFSoC-PYNQ/boards/ZCU111/petalinux\_bsp/meta-user/recipes-bsp/device-tree/files...](https://github.com/Xilinx/RFSoC-PYNQ/tree/master/boards/ZCU111/petalinux_bsp/meta-user/recipes-bsp/device-tree/files)**
>
> Python productivity for RFSoC platforms. Contribute to Xilinx/RFSoC-PYNQ development by creating an account on GitHub.

What you’re trying to achieve is possible, but it will require work to debug and put everything in place.

---

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [November 22, 2024, 6:43pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/5 "2024-11-22T18:43:30Z")

</div>

Yes, is in the first part of the dtsi file.

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [November 22, 2024, 7:01pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/6 "2024-11-22T19:01:52Z")

</div>

In that case, I would suggest you decompile the final system.dtb and check if these nodes were assigned correctly, clock names match, interrupt numbers match and so on.

---

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [November 25, 2024, 9:36am UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/7 "2024-11-25T09:36:41Z")

</div>

Ok, i will try but will be not easy. Here attached two decompiled dtb file, PYNQ.system.txt generated from RF-PYNQ repository (not working), and PETALINUX\_system.txt generated only with Petalinux (working).

Clearly there are several differences.

[PETALINUX\_system.txt](https://discuss.pynq.io/uploads/short-url/fac9h1cdHUkAXw4VrzaWUV0C7Xe.txt) (58.7 KB)  
[PYNQ\_system.txt](https://discuss.pynq.io/uploads/short-url/8eK4UYuWLVQOpw1fkleSQeGUCf9.txt) (57.1 KB)

Thanks,  
Federico

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [November 25, 2024, 2:57pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/8 "2024-11-25T14:57:32Z")

</div>

The most important part is that the `amba_pl@0`, `dma@a0000000` and `ethernet@a0040000` nodes are missing from the PYNQ device tree.

You need to add these nodes as part of the user configuration.

---

<div class="post-metadata">

**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\
**Post date:** [November 27, 2024, 4:42pm UTC](https://discuss.pynq.io/t/on-board-sfp-with-zcu111-and-pynq/7757/9 "2024-11-27T16:42:00Z")

</div>

Just an update…  
If i try to add missing nodes with dtsi user file the compilation stop because those nodes are already present:

> ERROR (duplicate\_label): /amba\_pl@0/ethernet@a0040000: Duplicate label ‘axi\_ethernet\_0’ on /amba\_pl@0/ethernet@a0040000 and /fragment@2/ **overlay** /ethernet@a0040000

I can see also from pl.dtsi (generated in /petalinux\_project/components/plnx\_workspace/device-tree/device-tree) that nodes are present:

```
fragment@2 {
	target = <&amba>;
	overlay2: __overlay__ {
		#address-cells = <2>;
		#size-cells = <2>;
		axi_dma_0: dma@a0000000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
			compatible = "xlnx,eth-dma";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4 0 90 4>;
			reg = <0x0 0xa0000000 0x0 0x10000>;
			xlnx,addrwidth = /bits/ 8 <0x20>;
			xlnx,include-dre ;
			xlnx,num-queues = /bits/ 16 <0x1>;
		};
		axi_ethernet_0: ethernet@a0040000 {
			axistream-connected = <&axi_dma_0>;
			axistream-control-connected = <&axi_dma_0>;
			clock-frequency = <100000000>;
			clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk";
			clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 72>;
			compatible = "xlnx,axi-ethernet-7.2", "xlnx,axi-ethernet-1.00.a";
			device_type = "network";
			interrupt-names = "interrupt", "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 91 4 0 89 4 0 90 4>;
			local-mac-address = [00 0a 35 00 00 00];
			phy-handle = <&axi_ethernet_0phy2>;
			phy-mode = "1000base-x";
			reg = <0x0 0xa0040000 0x0 0x40000>;
			xlnx = <0x0>;
			xlnx,axiliteclkrate = <0x0>;
			xlnx,axisclkrate = <0x0>;
			xlnx,channel-ids = <0x1>;
			xlnx,clockselection = <0x0>;
			xlnx,enableasyncsgmii = <0x0>;
			xlnx,gt-type = <0x0>;
			xlnx,gtinex = <0x0>;
			xlnx,gtlocation = <0x0>;
			xlnx,gtrefclksrc = <0x0>;
			xlnx,include-dre ;
			xlnx,instantiatebitslice0 = <0x0>;
			xlnx,num-queues = /bits/ 16 <0x1>;
			xlnx,phy-type = <0x5>;
			xlnx,phyaddr = <0x2>;
			xlnx,phyrst-board-interface-dummy-port = <0x0>;
			xlnx,rable = <0x0>;
			xlnx,rxcsum = <0x2>;
			xlnx,rxlane0-placement = <0x0>;
			xlnx,rxlane1-placement = <0x0>;
			xlnx,rxmem = <0x8000>;
			xlnx,rxnibblebitslice0used = <0x0>;
			xlnx,tx-in-upper-nibble = <0x1>;
			xlnx,txcsum = <0x2>;
			xlnx,txlane0-placement = <0x0>;
			xlnx,txlane1-placement = <0x0>;
			xlnx,versal-gt-board-flow = <0x0>;
			zclock-names = "NULL";
			zclocks = "NULL";
			axi_ethernet_0_mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				axi_ethernet_0phy2: phy@2 {
					device_type = "ethernet-phy";
					reg = <2>;
				};
			};
		};
	};

```

But for some unknown reason in the compiled device tree .dtb segments disappear.

I tried also to disable FPGA manager, in this case during the boot the ethernet link to the SFP module became up but the boot stop at: Loading kernel…

I’m in a real frustrating situation. Any suggestions will be appreciate…

Federico