PYNQ: PYTHON PRODUCTIVITY

Only one interface of U280 is normal after dowloading XUP example

Sorry for not replying to @marioruiz for a long time as there is a problem with U280 power, and the original topic is closed, so I create this.

After I download .xclbin of XUP to U280 (two interfaces are connected to the switch via two qsfp28 Tansceiver modules and a cable), and use the vnx-basic.ipynb to configure the FPGA, there is only one of the two network interfaces is UP.
The make command:

make all DEVICE=<full platform path> INTERFACE=<interface number> DESIGN=<design name>

the result of vnx-basic.ipynb is

Link interface 0 {'cmac_link': True}; link interface 1 {'cmac_link': False}

Then I adjust the interface connecting scheme from 1 to 2:

The result of vnx-basic.ipynb doesn’t change.

So the problem occurs in interface 1. Are there some solutions?

Thanks a lot for your help.

We already discussed about this on GitHub One of the two network interfaces of U280 is down · Issue #33 · Xilinx/xup_vitis_network_example · GitHub

It seems to be a problem with the board