# Overlay load fail: No cached metadata present

**URL:** <https://discuss.pynq.io/t/overlay-load-fail-no-cached-metadata-present/7842>\
**Category:** Support\
**Created:** [December 16, 2024, 1:43pm UTC](https://discuss.pynq.io/t/overlay-load-fail-no-cached-metadata-present/7842 "2024-12-16T13:43:45Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![nibbs](https://avatars.discourse-cdn.com/v4/letter/n/f05b48/32.png) [@nibbs](https://discuss.pynq.io/u/nibbs)\
**Post date:** [December 16, 2024, 1:43pm UTC](https://discuss.pynq.io/t/overlay-load-fail-no-cached-metadata-present/7842/1 "2024-12-16T13:43:45Z")

</div>

I execute a cell with:  
from pynq import Overlay  
from pynq import allocate  
import xrfclk  
import xrfdc  
ol = Overlay(“./RFADC\_DMA2.bit”)

The current directory contains the above bit file plus RFADC\_DMA2.hwh (from …\*\*.gen/sources\_1/bd/mpsoc\_preset/hw\_handoff/ ) and RFADC\_DMA2.tcl (created by exporting the block diagram) from my Vivado project (2023.2).  
Anyone suggest what I am missing?  
thanks.

* * *

CacheMetadataError Traceback (most recent call last)  
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:252, in BitstreamHandler.get\_parser(self, partial)  
251 try:  
 → 252 parser = self.\_get\_cache()  
253 except CacheMetadataError:

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:228, in BitstreamHandler.\_get\_cache(self)  
227 else:  
 → 228 raise CacheMetadataError(f"No cached metadata present")

CacheMetadataError: No cached metadata present

During handling of the above exception, another exception occurred:

MetadataObjectNotFound Traceback (most recent call last)  
Input In [42], in \<cell line: 5\>()  
3 import xrfclk  
4 import xrfdc  
----\> 5 ol = Overlay(“./RFADC\_DMA2.bit”)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay. **init** (self, bitfile\_name, dtbo, download, ignore\_version, device, gen\_cache)  
315 super(). **init** (bitfile\_name, dtbo, partial=False, device=device)  
317 self.\_register\_drivers()  
 → 319 self.device.set\_bitfile\_name(self.bitfile\_name)  
320 self.parser = self.device.parser  
322 self.ip\_dict = (  
323 self.gpio\_dict  
324 ) = (  
325 self.interrupt\_controllers  
326 ) = self.interrupt\_pins = self.hierarchy\_dict = dict()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/device.py:118, in Device.set\_bitfile\_name(self, bitfile\_name)  
116 def set\_bitfile\_name(self, bitfile\_name: str) → None:  
117 self.bitfile\_name = bitfile\_name  
 → 118 self.parser = self.get\_bitfile\_metadata(self.bitfile\_name)  
119 self.mem\_dict = self.parser.mem\_dict  
120 self.ip\_dict = self.parser.ip\_dict

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:690, in EmbeddedDevice.get\_bitfile\_metadata(self, bitfile\_name, partial)  
689 def get\_bitfile\_metadata(self, bitfile\_name:str, partial:bool=False):  
 → 690 parser = \_get\_bitstream\_handler(bitfile\_name).get\_parser(partial=partial)  
691 if parser is None:  
692 raise RuntimeError(“Unable to find metadata for bitstream”)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:254, in BitstreamHandler.get\_parser(self, partial)  
252 parser = self.\_get\_cache()  
253 except CacheMetadataError:  
 → 254 parser = RuntimeMetadataParser(Metadata(input=self.\_filepath.with\_suffix(“.hwh”)))  
255 except:  
256 raise RuntimeError(f"Unable to parse metadata")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:40, in Metadata(input)  
38 if os.path.isfile(input):  
39 if str(input).endswith(“.hwh”):  
—\> 40 return HwhFrontend(\_hwhfile=input)  
41 elif str(input).endswith(“.xsa”):  
42 return XsaFrontend(input=input)

File :25, in **init** (self, name, type, generic\_type, \_parent, \_children, ref, ext, \_timestamp, hierarchy\_name, ports, parameters, blocks, modules, busses, \_hierarchies, \_hwhfile, \_element\_tree, \_root, \_logical2physical\_portmap, \_physical2logical\_portmap, \_logical2physical\_extern\_pm, \_physical2logical\_extern\_pm)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:219, in HwhFrontend. **post\_init** (self)  
207 “”"  
208 Performs the parsing of the hwh into the metadata model  
209 \* checks to see if the hwhfile is an XML string or a  
(…)  
216 \* Performs a connectivity pass  
217 “”"  
218 if self.\_hwhfile != “”:  
 → 219 self.parse()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:241, in HwhFrontend.parse(self)  
238 self.\_create\_external\_ports()  
240 self.resolve\_addressing()  
 → 241 self.connect\_signals()  
243 self.refresh()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:657, in HwhFrontend.connect\_signals(self)  
653 dst\_signal = dst\_core.lookup(  
654 f"{dst\_portname}[port]:{dst\_signame}[signal]"  
655 )  
656 else:  
 → 657 dst\_signal = dst\_core.lookup(  
658 f"{c\_dst}[port]:{c\_dst}[signal]"  
659 )  
661 if isinstance(signal, Signal) and isinstance(dst\_signal, Signal):  
662 signal.connect(dst\_signal)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/metadata\_object.py:185, in MetadataObject.lookup(self, ref)  
183 return obj  
184 else:  
 → 185 raise MetadataObjectNotFound(  
186 f"{ref} cannot be found in {self.ref} children={self.\_children.keys()}"  
187 )

MetadataObjectNotFound: s\_axis\_s2mm\_tlast[port]:s\_axis\_s2mm\_tlast[signal] cannot be found in mpsoc\_preset:axi\_dma\_0[block] children=dict\_keys([‘C\_DLYTMR\_RESOLUTION[parameter]’, ‘C\_ENABLE\_MULTI\_CHANNEL[parameter]’, ‘C\_FAMILY[parameter]’, ‘C\_INCLUDE\_MM2S[parameter]’, ‘C\_INCLUDE\_MM2S\_DRE[parameter]’, ‘C\_INCLUDE\_MM2S\_SF[parameter]’, ‘C\_INCLUDE\_S2MM[parameter]’, ‘C\_INCLUDE\_S2MM\_DRE[parameter]’, ‘C\_INCLUDE\_S2MM\_SF[parameter]’, ‘C\_INCLUDE\_SG[parameter]’, ‘C\_INCREASE\_THROUGHPUT[parameter]’, ‘C\_MICRO\_DMA[parameter]’, ‘C\_MM2S\_BURST\_SIZE[parameter]’, ‘C\_M\_AXIS\_MM2S\_CNTRL\_TDATA\_WIDTH[parameter]’, ‘C\_M\_AXIS\_MM2S\_TDATA\_WIDTH[parameter]’, ‘C\_M\_AXI\_MM2S\_ADDR\_WIDTH[parameter]’, ‘C\_M\_AXI\_MM2S\_DATA\_WIDTH[parameter]’, ‘C\_M\_AXI\_S2MM\_ADDR\_WIDTH[parameter]’, ‘C\_M\_AXI\_S2MM\_DATA\_WIDTH[parameter]’, ‘C\_M\_AXI\_SG\_ADDR\_WIDTH[parameter]’, ‘C\_M\_AXI\_SG\_DATA\_WIDTH[parameter]’, ‘C\_NUM\_MM2S\_CHANNELS[parameter]’, ‘C\_NUM\_S2MM\_CHANNELS[parameter]’, ‘C\_PRMRY\_IS\_ACLK\_ASYNC[parameter]’, ‘C\_S2MM\_BURST\_SIZE[parameter]’, ‘C\_SG\_INCLUDE\_STSCNTRL\_STRM[parameter]’, ‘C\_SG\_LENGTH\_WIDTH[parameter]’, ‘C\_SG\_USE\_STSAPP\_LENGTH[parameter]’, ‘C\_S\_AXIS\_S2MM\_STS\_TDATA\_WIDTH[parameter]’, ‘C\_S\_AXIS\_S2MM\_TDATA\_WIDTH[parameter]’, ‘C\_S\_AXI\_LITE\_ADDR\_WIDTH[parameter]’, ‘C\_S\_AXI\_LITE\_DATA\_WIDTH[parameter]’, ‘Component\_Name[parameter]’, ‘c\_addr\_width[parameter]’, ‘c\_dlytmr\_resolution[parameter]’, ‘c\_enable\_multi\_channel[parameter]’, ‘c\_include\_mm2s[parameter]’, ‘c\_include\_mm2s\_dre[parameter]’, ‘c\_include\_mm2s\_sf[parameter]’, ‘c\_include\_s2mm[parameter]’, ‘c\_include\_s2mm\_dre[parameter]’, ‘c\_include\_s2mm\_sf[parameter]’, ‘c\_include\_sg[parameter]’, ‘c\_increase\_throughput[parameter]’, ‘c\_m\_axi\_mm2s\_data\_width[parameter]’, ‘c\_m\_axi\_s2mm\_data\_width[parameter]’, ‘c\_m\_axis\_mm2s\_tdata\_width[parameter]’, ‘c\_micro\_dma[parameter]’, ‘c\_mm2s\_burst\_size[parameter]’, ‘c\_num\_mm2s\_channels[parameter]’, ‘c\_num\_s2mm\_channels[parameter]’, ‘c\_prmry\_is\_aclk\_async[parameter]’, ‘c\_s2mm\_burst\_size[parameter]’, ‘c\_s\_axis\_s2mm\_tdata\_width[parameter]’, ‘c\_sg\_include\_stscntrl\_strm[parameter]’, ‘c\_sg\_length\_width[parameter]’, ‘c\_sg\_use\_stsapp\_length[parameter]’, ‘c\_single\_interface[parameter]’, ‘EDK\_IPTYPE[parameter]’, ‘C\_BASEADDR[parameter]’, ‘C\_HIGHADDR[parameter]’, ‘ADDR\_WIDTH[parameter]’, ‘ARUSER\_WIDTH[parameter]’, ‘AWUSER\_WIDTH[parameter]’, ‘BUSER\_WIDTH[parameter]’, ‘CLK\_DOMAIN[parameter]’, ‘DATA\_WIDTH[parameter]’, ‘FREQ\_HZ[parameter]’, ‘HAS\_BRESP[parameter]’, ‘HAS\_BURST[parameter]’, ‘HAS\_CACHE[parameter]’, ‘HAS\_LOCK[parameter]’, ‘HAS\_PROT[parameter]’, ‘HAS\_QOS[parameter]’, ‘HAS\_REGION[parameter]’, ‘HAS\_RRESP[parameter]’, ‘HAS\_WSTRB[parameter]’, ‘ID\_WIDTH[parameter]’, ‘INSERT\_VIP[parameter]’, ‘MAX\_BURST\_LENGTH[parameter]’, ‘NUM\_READ\_OUTSTANDING[parameter]’, ‘NUM\_READ\_THREADS[parameter]’, ‘NUM\_WRITE\_OUTSTANDING[parameter]’, ‘NUM\_WRITE\_THREADS[parameter]’, ‘PHASE[parameter]’, ‘PROTOCOL[parameter]’, ‘READ\_WRITE\_MODE[parameter]’, ‘RUSER\_BITS\_PER\_BYTE[parameter]’, ‘RUSER\_WIDTH[parameter]’, ‘SUPPORTS\_NARROW\_BURST[parameter]’, ‘WUSER\_BITS\_PER\_BYTE[parameter]’, ‘WUSER\_WIDTH[parameter]’, ‘HAS\_TKEEP[parameter]’, ‘HAS\_TLAST[parameter]’, ‘HAS\_TREADY[parameter]’, ‘HAS\_TSTRB[parameter]’, ‘LAYERED\_METADATA[parameter]’, ‘TDATA\_NUM\_BYTES[parameter]’, ‘TDEST\_WIDTH[parameter]’, ‘TID\_WIDTH[parameter]’, ‘TUSER\_WIDTH[parameter]’, ‘S\_AXI\_LITE[port]’, ‘M\_AXI\_SG[port]’, ‘M\_AXI\_S2MM[port]’, ‘S\_AXIS\_S2MM[port]’, ‘S\_AXIS\_STS[port]’, ‘axi\_resetn[port]’, ‘m\_axi\_s2mm\_aclk[port]’, ‘m\_axi\_sg\_aclk[port]’, ‘s2mm\_introut[port]’, ‘s2mm\_prmry\_reset\_out\_n[port]’, ‘s2mm\_sts\_reset\_out\_n[port]’, ‘s\_axi\_lite\_aclk[port]’])

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<div class="post-metadata">

**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\
**Post date:** [December 16, 2024, 6:32pm UTC](https://discuss.pynq.io/t/overlay-load-fail-no-cached-metadata-present/7842/2 "2024-12-16T18:32:03Z")

</div>

Hi,  
Which board are you using?

Can you please provide the Vivado architecture you are using (.tcl, .bit and .hwh)?

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<div class="post-metadata">

**Author:** ![nibbs](https://avatars.discourse-cdn.com/v4/letter/n/f05b48/32.png) [@nibbs](https://discuss.pynq.io/u/nibbs)\
**Post date:** [December 17, 2024, 9:31am UTC](https://discuss.pynq.io/t/overlay-load-fail-no-cached-metadata-present/7842/3 "2024-12-17T09:31:48Z")

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Hi,  
I am using the ZCU208 and starting to learn about Pynq. I had tried a few years ago and couldn’t get things to work so have been using KoheronSDK for about a decade (which incidentally works very nicely). I have attached the files in question[RFADC\_DMA2.hwh](https://discuss.pynq.io/uploads/short-url/2KLF5lFseKNcqwEsI2lAz3wU7us.hwh) (494.0 KB)  
[RFADC\_DMA2.tcl](https://discuss.pynq.io/uploads/short-url/iQZTfzb9OxnzjKWRNoBCK89TlsS.tcl) (38.0 KB)  
Unfortunately the .bit file looks too be to big to post, but I guess can be generated from the tcl file. I was trying to connect up the RFSoC ADC to a DMA block to try reading ADC data. I have since started a new design from scratch and that now seems to load OK, so not sure what the issue was. The error messages from Xilinx software don’t seem to be very helpful (or at least you need to be a super sleuth to figure them out lol). cheers G
