# Parse hwh file failed **URL:** \ **Category:** Support\ **Created:** [August 30, 2021, 9:21am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975 "2021-08-30T09:21:04Z")\ **Posts on this page:** 11\ **Page:** 1
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [August 30, 2021, 9:21am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/1 "2021-08-30T09:21:04Z")
Hi, I want to make a custom overlay on zcu104. I am using pynq 2.6 and vivado 2020.2. But when I load the bitstream, the .hwh file cannot be parsed properly. The error message is shown as follows. ![Screenshot 2021-08-30 at 4.41.48 PM](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/26536cd0c71291692688b9504baf096018a2bd9a.png) ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 30, 2021, 4:04pm UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/2 "2021-08-30T16:04:36Z")
Hi @Hongduo_Liu, Can you post an image of the block design? Can you also share the hwh file? pynq 2.6 has been validated with Vivado 2020.1, so there may be an issue with Vivado versions Mario ---
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [August 31, 2021, 3:28am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/4 "2021-08-31T03:28:42Z")
Hi marioruiz, Please see attached. Regarding the version concern, I will try to use 2020.1 to generate the bitstream and hwh file. [my.hwh](https://discuss.pynq.io/uploads/short-url/iXAYn6M5lZlvD3xz8ejHuAnXDUY.hwh) (1.1 MB) [schematic.pdf](https://discuss.pynq.io/uploads/short-url/kQoyUSH11BTOGtFlHJPwa6aE6sq.pdf) (488.1 KB) ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [August 31, 2021, 7:51am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/5 "2021-08-31T07:51:43Z")
The elaborated RTL you provide is difficult to navigate and it is not possible to zoom in enough. I had a look at the hwh file and it seems that an interrupt controller is not present. `pynq` does not support interrupts connected directly to the PS. You need an interrupt controller. Some documentation here [https://pynq.readthedocs.io/en/v2.6.1/overlay\_design\_methodology/pspl\_interface.html#interrupt](https://pynq.readthedocs.io/en/v2.6.1/overlay_design_methodology/pspl_interface.html#interrupt) > [@Zynq PS7 Interrupts](https://discuss.pynq.io/t/zynq-ps7-interrupts/198/2): > > Interrupts are an area that is causing confusing and I’m working on creating some better documentation for them. I’ve also noticed some bugs in the code that can potentially cause spurious interrupt responses that I’m working to fix. In the meantime, I’ve pasted below an example I’m working on in the hope it can be of use to you - just remember it is a work in progress. One thing I will highlight relevant to your example is that we only support interrupts that are ultimately connected to IRQ\_F2… > [@Interrupt error on using two VDMA](https://discuss.pynq.io/t/interrupt-error-on-using-two-vdma/2700/4): > > PYNQ does not support the interrupts to be connected like that. You need an interrupt controller [https://pynq.readthedocs.io/en/v2.6.1/overlay\_design\_methodology/pspl\_interface.html#interrupt](https://pynq.readthedocs.io/en/v2.6.1/overlay_design_methodology/pspl_interface.html#interrupt) Something like this Mario Mario ---
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [September 1, 2021, 6:43am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/6 "2021-09-01T06:43:48Z")
After adding the interrupt controller, I could load the bitstream properly. However, PYNQ cannot find all the IPs. For example, the axi\_dma IP. Does PYNQ support multiple axi\_dma IPs? If the answer is yes, what’s could be the reason for only accessing two IPs? ![Screenshot 2021-09-01 at 2.39.28 PM](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/320ef99393ee3ed661ad49145748fb31b0656276.png) ---
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [September 1, 2021, 6:46am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/7 "2021-09-01T06:46:15Z")
Here only two IPs are addressed. Since I cannot access AXI\_DMA IP, I cannot transfer data from PS to PL. ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [September 1, 2021, 7:18am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/8 "2021-09-01T07:18:25Z")
Yes, PYNQ supports multiple DMA Without seeing the IP Integrator block design and the new hwh file it is difficult to say if something is missing. ---
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [September 1, 2021, 9:15am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/9 "2021-09-01T09:15:00Z")
I provide the schematic of the block design and the hwh file for reference. Thank you.[design.hwh](https://discuss.pynq.io/uploads/short-url/vRLVkTvV1UsqqgNwaNYuNgiMs7r.hwh) (1.2 MB) [schematic.pdf](https://discuss.pynq.io/uploads/short-url/9m833V0GjpNkdMyt4TfktgKB596.pdf) (362.9 KB) ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [September 1, 2021, 9:34am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/10 "2021-09-01T09:34:59Z")
You are providing the Elaborated schematics. I’d like to see the IP Integrator block design. Something like this [https://forums.xilinx.com/t5/image/serverpage/image-id/15298i333887E012E58F09?v=v2](https://forums.xilinx.com/t5/image/serverpage/image-id/15298i333887E012E58F09?v=v2) ---
**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\ **Post date:** [September 1, 2021, 1:49pm UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/11 "2021-09-01T13:49:24Z")
Trying to reverse engineer your HWH files it appears you don’t connect the dma engines to the PS so there is no way for PYNQ to interact with them - they’re driven directly by the `DMA_Read_Control` blocks. As they’re not in the address space of the PS they won’t appear in the overlay. ---
**Author:** ![Hongduo\_Liu](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/hongduo_liu/32/2303_2.png) [@Hongduo\_Liu](https://discuss.pynq.io/u/Hongduo_Liu)\ **Post date:** [September 2, 2021, 9:43am UTC](https://discuss.pynq.io/t/parse-hwh-file-failed/2975/12 "2021-09-02T09:43:56Z")
I think this reason really makes sense. If it is not practical to modify this design, I guess the only option is to use zynq? Any suggestions are greatly appreciated.