# Phase jump with ADC acquisition on RFSOC board **URL:** \ **Category:** Support\ **Created:** [June 20, 2023, 12:07pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721 "2023-06-20T12:07:42Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\ **Post date:** [June 20, 2023, 12:07pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/1 "2023-06-20T12:07:42Z")
Hi folks! i working with a ZCU111 (pynq firmware v2.7) board since several time but i’m not a real expert with SOC, now i’m in stuck because i’m trying to acquire a signal with the ADC on board (schematic here attached [rfsoc.pdf](https://discuss.pynq.io/uploads/short-url/pkpvAvdV4LUMCfsycF9m05YoBrh.pdf) (166.4 KB) ). The signal generation with the DAC is working well and also the acquisition but only for the first 1024 byte (exactly the FIFO depth) after there is a sort of phase jump every beginning of 1024 new block. Here the screenshot of IP configuration: ![Cap_1](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/32c3f1c146661366bae71f9e786feaf213c6544b.png) ![Cap_2](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/1200d58efdc218434cf4ae343636f0b4279d3540.png) ![Cap_3](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/eceebdf5eee5e440aaffa1c49c74d20bc1785ea2.png) ![Cap_4](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/05d76a6eb9a3ba6f4004cc1ea362a15328375ace.png) ![Cap_5](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c6b5280f579187ec48c22230d0a12ceab8052666.png) Here the code: ![Cap_6](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/0b1d1727aa0d0fc3bfc3ee80d3516b2910e157ab.png) and a detail of the problem: ![acq](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3729d74633bba97690452c395d21d26d832bde0d.gif) If i increase the FIFO depth the behaviour is the same after the new ammount of memory available. Does anyone have a suggestion on where to look? Sorry if the question is little bit out of forum topic Thank you. Federico ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 20, 2023, 1:14pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/2 "2023-06-20T13:14:57Z")
Hi @Federico, Welcome to the PYNQ community. This topic has been discussed previously here > [@Store data from PL (ADC) to PS via DMA in ZCU111](https://discuss.pynq.io/t/store-data-from-pl-adc-to-ps-via-dma-in-zcu111/4928): > > Hi there! I am Jorge. I am currently developing software/hardware with the ZCU111 board. I am using PYNQ version 2.7. My goal is the following: I am acquiring an RF signal through the ADC on the PL and I want to receive it on the PS. For this, I have used the following schematic: SCHEMATIC: AXI DMA block config: Subset Converter block config: FIFO block config: At the moment, I am only using one channel. The RF Data Converter acquires the signa… Best, Mario ---
**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\ **Post date:** [June 20, 2023, 3:01pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/3 "2023-06-20T15:01:15Z")
Hi @marioruiz , thank you for replying me. I appreciate it. I saw that post but unfortunately i don’t have a good experience with FIFO and DMA transaction, could you explain me more in details? Thanks, Federico ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [June 20, 2023, 6:11pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/4 "2023-06-20T18:11:53Z")
Hi @Federico, There’s a wide breadth of DMA tutorial and resources in this forums. I suggest you start by looking at these series: > [@Tutorial: PYNQ DMA (Part 1: Hardware design)](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133): > > PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. … > [@Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344): > > Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design) In a [previous tutorial](https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133) I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, [part 2](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-tutorial-part-2-vivado-design/3345) shows how to build the Vivad… Mario ---
**Author:** ![Federico](https://avatars.discourse-cdn.com/v4/letter/f/c2a13f/32.png) [@Federico](https://discuss.pynq.io/u/Federico)\ **Post date:** [June 20, 2023, 6:15pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/5 "2023-06-20T18:15:40Z")
Thanks @marioruiz, i will do it! Federico ---
**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\ **Post date:** [June 20, 2023, 10:47pm UTC](https://discuss.pynq.io/t/phase-jump-with-adc-acquisition-on-rfsoc-board/5721/6 "2023-06-20T22:47:59Z")
@marioruiz @Federico Had read ij0r explain and sounds like a ping-pong buffer is more suitable. His explanation simply said the next DMA request is not N but N-FIFO\_SIZE. But the final Stream\_Size request is N, such that this cannot simply use default API to complete the job. Hum, interesting that do the default IP from Vivado got IP could make this work w/o using HLS? ENJOY~