Phase jump with ADC acquisition on RFSOC board

Hi folks!
i working with a ZCU111 (pynq firmware v2.7) board since several time but i’m not a real expert with SOC, now i’m in stuck because i’m trying to acquire a signal with the ADC on board (schematic here attached
rfsoc.pdf (166.4 KB)
The signal generation with the DAC is working well and also the acquisition but only for the first 1024 byte (exactly the FIFO depth) after there is a sort of phase jump every beginning of 1024 new block.

Here the screenshot of IP configuration:

Here the code:

and a detail of the problem:


If i increase the FIFO depth the behaviour is the same after the new ammount of memory available.

Does anyone have a suggestion on where to look? Sorry if the question is little bit out of forum topic
Thank you.

Hi @Federico,

Welcome to the PYNQ community.

This topic has been discussed previously here


Hi @marioruiz ,
thank you for replying me. I appreciate it. I saw that post but unfortunately i don’t have a good experience with FIFO and DMA transaction, could you explain me more in details?

Hi @Federico,

There’s a wide breadth of DMA tutorial and resources in this forums. I suggest you start by looking at these series:


Thanks @marioruiz, i will do it!

@marioruiz @Federico

Had read ij0r explain and sounds like a ping-pong buffer is more suitable.
His explanation simply said the next DMA request is not N but N-FIFO_SIZE.
But the final Stream_Size request is N, such that this cannot simply use default API to complete the job.
Hum, interesting that do the default IP from Vivado got IP could make this work w/o using HLS?