# Ported my working Pynq2.4 project to Pynq 2.5 and it nows crashes on VDMA read **URL:** \ **Category:** Support\ **Created:** [March 17, 2020, 11:30am UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029 "2020-03-17T11:30:45Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![DarthSimpson](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/darthsimpson/32/743_2.png) [@DarthSimpson](https://discuss.pynq.io/u/DarthSimpson)\ **Post date:** [March 17, 2020, 11:30am UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029/1 "2020-03-17T11:30:45Z")
Hi there, Any one have issues with VDMA engines in Pynq 2.5. I ported a working project from 2.4 (Ultra96) to 2.5 (ZCU102), also migrating to vivado 19.1. # Setting up the VMDA driver PL\_vdma = overlay.axi\_vdma\_0 framemode = VideoMode(1280, 720, 24) # Set the read channel parameters to the capture specifications and enable the VDMA PL\_vdma.readchannel.mode = framemode # I have a couple of selectable axi stream swtiches # Set for normal passthrough set\_path\_pipeline(1) # set to test pattern set\_source\_pipeline(2) **PL\_vdma.readchannel.start()** frame\_tp = PL\_vdma.readchannel.readframe() PL\_vdma.readchannel.stop() frame\_color\_tp=cv2.cvtColor(frame\_tp,cv2.COLOR\_BGR2RGB) pixels\_tp = np.array(frame\_color\_tp) plt.imshow(pixels\_tp) plt.show() # set to webcamera source set\_source\_pipeline(1) As soon as i call PL\_vdma.readchannel.start() Pynq and the entire board crashes / stalls. Any idea what the problem might be. See attached notebook as well… Darth [video\_pipeline-8.ipynb](https://discuss.pynq.io/uploads/short-url/8LKgMEak8AwUmBNHTDrRoqV4Nvz.ipynb) (22.9 KB) ---
**Author:** ![rock](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rock/32/32_2.png) [@rock](https://discuss.pynq.io/u/rock)\ **Post date:** [March 17, 2020, 4:04pm UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029/2 "2020-03-17T16:04:50Z")
I am guessing (only guessing) it might be the PS configurations differ from the 2 versions. Maybe you can check the AXI port width for your old image and the new image. When you download bitstream, the PS configuration does not get changed (except the PL clocks). e.g. check Register(0xFF419000)[9:8] to see if they are the same. ---
**Author:** ![DarthSimpson](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/darthsimpson/32/743_2.png) [@DarthSimpson](https://discuss.pynq.io/u/DarthSimpson)\ **Post date:** [March 17, 2020, 4:46pm UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029/3 "2020-03-17T16:46:54Z")
I have a simple adder ip block and it works ok. I did tweak things a bit, like the address space for the vdma blocks, now that theres is 4GB of DDR4 vs 2GB on the Ultra96. ![Capture](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/2c17304efbe5fbbb66f1ebd3e0c415bde2acfefb.png) ![Capture2](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/35418c45a35e0ece21f8d0437c5ed2dfad240d25.png) ![Capture3](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/20a3b0d4136326a37b9f263cf34886a80fcac2e9.png) ---
**Author:** ![rock](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rock/32/32_2.png) [@rock](https://discuss.pynq.io/u/rock)\ **Post date:** [March 18, 2020, 4:50am UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029/4 "2020-03-18T04:50:48Z")
I think you might check the 2 tcl files that are used to generate the block design, or the PS configuration in your block design. Double check the memory port (enabled or not, port width) to make sure they are correct. Also find the PS configuration in the ZCU102 bsp, and make sure the configuration is correct; this is because the PYNQ image always uses the PS configurations from the petalinux bsp after boot. If not, you may need to adjust some register values. ---
**Author:** ![DarthSimpson](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/darthsimpson/32/743_2.png) [@DarthSimpson](https://discuss.pynq.io/u/DarthSimpson)\ **Post date:** [March 20, 2020, 2:28pm UTC](https://discuss.pynq.io/t/ported-my-working-pynq2-4-project-to-pynq-2-5-and-it-nows-crashes-on-vdma-read/1029/5 "2020-03-20T14:28:53Z")
HI Rock, Managed to get it working by replicating the memoroy space for the Ultra96 and not defined memroy segment HP0\_DDR\_HIGH. I also limited the VDMA address bits to 32bits… Darth ![Capture](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/f38626a8f1090d345e931527f39e4f64ada712c0.png) ![Capture2](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/176ed9847d283ef0dfadad0a8da5af6b04dcb559.png) ![Capture3](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/458292b3737e68ff8274c4844a4c4fe21721620c.png)