# Problem with Zynq UltraScale MPSoC Cache Coherency

**URL:** <https://discuss.pynq.io/t/problem-with-zynq-ultrascale-mpsoc-cache-coherency/4375>\
**Category:** Support\
**Created:** [June 22, 2022, 1:39pm UTC](https://discuss.pynq.io/t/problem-with-zynq-ultrascale-mpsoc-cache-coherency/4375 "2022-06-22T13:39:43Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![atopet](https://avatars.discourse-cdn.com/v4/letter/a/85f322/32.png) [@atopet](https://discuss.pynq.io/u/atopet)\
**Post date:** [June 22, 2022, 1:39pm UTC](https://discuss.pynq.io/t/problem-with-zynq-ultrascale-mpsoc-cache-coherency/4375/1 "2022-06-22T13:39:43Z")

</div>

I am currently facing a problem with deploying a model and after tracing I found out that the problem may be related to Zynq UltraScale MPSoC Cache Coherency.

I have successfully created a custom pynqv2.6 image using a bionic agonistic file and BSP for zcu102 as this is the version currently supported by the Apache TVM DL. However, when running a test model, it got stuck at ‘load module’ with default parameters. But when the COHERENT\_ACCESSES is changed to false, it runs normal but with a wrong output/prediction.

Could this possibly be a problem with the image creation phase or is there any possible support to fix this?