# Program LMK&LMX on RFSoC4x2 from Vitis(No PYNQ) **URL:** \ **Category:** Support\ **Created:** [May 5, 2025, 11:08am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383 "2025-05-05T11:08:07Z")\ **Posts on this page:** 16\ **Page:** 1
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 5, 2025, 11:08am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/1 "2025-05-05T11:08:07Z")
I’m trying to use RFSoC4x2 to build a RF receiver. The RFDC is driven by LMK&LMX chips, they are programmed by PS through SPI. I have generated the register values from TICS pro, and use ‘XSpiPs\_PolledTransfer’ function in Vitis to program LMK and LMX. The two LMX are programmed with same value, but it is very strange that only PLL2(for DAC) can be programmed, PLL1(for ADC) and LMK does not repond, the LEDs on board is off, and I used ILA in vivado, PLL1 clock is not working. I have been working on this problem for 2 weeks but no prograss, please help me! [LMK\_LMX.c](https://discuss.pynq.io/uploads/short-url/jTz8icU78ydGnfOClfCzI5tkn2o.c) (12.8 KB) [LMK\_LMX.h](https://discuss.pynq.io/uploads/short-url/4tBrlXdTILifqaHyyJRuZiF9mrx.h) (805 Bytes) ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 6, 2025, 8:33pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/2 "2025-05-06T20:33:54Z")
Hi, I haven’t check your whole library yet. May I ask is there any particular reason, you don’t want to use [xrfclk](https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/board_common/src/rfclk/src) library? Best ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 7, 2025, 4:32am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/3 "2025-05-07T04:32:08Z")
Hello, Thanks for your reply. The xrfclk library is designed for Zed board series, which use I2C to program the clocks. I’m using RFSoC4x2, and this board use SPI to program clock, they are not same thing, so I can’t use xrfclk library you mentioned to write to LMK and LMX. ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 7, 2025, 7:45pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/4 "2025-05-07T19:45:32Z")
Hi, I understand the issue. The leds can be on or off based on your TICS PRO file (I had the similar issue, check [RFSoC 4x2 PLL Lock Leds don’t turn on](https://discuss.pynq.io/t/rfsoc-4x2-pll-lock-leds-dont-turn-on/8063). Can you tell me whether you changed the registers for DAC in LMK? What is your clock speed for all? Is PLL enabled in block design? Since DAC PLL is working, that might be wrong configuration in either of them. Best ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 8, 2025, 5:23am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/5 "2025-05-08T05:23:40Z")
Hi, The shortcut of my settings in TICS pro is shown in Figure 1-4 in the attachment, I think the LEDs are set to show lock state, not for read back, register values are attached in txt file. Output clock for LMK is 250MHz and send to both LMX, Output clock for LMX is 5GHz for both ADC and DAC. PLL is not enabled in block design in Vivado, will this have any effect? I also tried to use other people’s register values from [RFSoC-PYNQ/boards/RFSoC4x2/packages/tics/tics/register\_txts/LMX2594\_491.52.txt at master · Xilinx/RFSoC-PYNQ · GitHub](https://github.com/Xilinx/RFSoC-PYNQ/blob/master/boards/RFSoC4x2/packages/tics/tics/register_txts/LMX2594_491.52.txt) But none of them worked, the LEDs on board just won’t turn on. My SPI clock is set in Vivado, which is 20MHz, shown in Figure 5. and I use ‘XSpiPs\_SetClkPrescaler(SpiInstancePtr, XSPIPS\_CLK\_PRESCALE\_16)’ to divide the clock, so the actual SPI clock should be 1.25MHz. I’m not sure which part went wrong. Thanks! [figures.pdf](https://discuss.pynq.io/uploads/short-url/3SKXpZOdjXkcrq03xWJ3YCtaYjO.pdf) (804.5 KB) ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 8, 2025, 5:24am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/6 "2025-05-08T05:24:34Z")
This is the reg values [LMK and LMX reg value.txt](https://discuss.pynq.io/uploads/short-url/ega43VkIm87Vq252Ms52aQ6jK9y.txt) (3.6 KB) ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 8, 2025, 3:55pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/7 "2025-05-08T15:55:47Z")
Hi, Thanks for the detailed explanation. I check your code again, I believe you need to add look up for SPI ID and I don’t see any initialization for your SPI, that might be another issue. Check out [Adam Taylor SPI example](https://github.com/ATaylorCEngFIET/Part_217_SPI_Master_Salve/blob/master/project_1/project_1.sdk/spi_ps/src/helloworld.c), it might give you some insight about error. > [@zuyuan\_xing](#): > > Output clock for LMK is 250MHz and send to both LMX, Output clock for LMX is 5GHz for both ADC and DAC. I think you need to check your clocks again. I check the values on PYNQ as well, unfortunately, PLLs don’t lock. > [@zuyuan\_xing](#): > > My SPI clock is set in Vivado, which is 20MHz, shown in Figure 5. > > and I use ‘XSpiPs\_SetClkPrescaler(SpiInstancePtr, XSPIPS\_CLK\_PRESCALE\_16)’ to divide the clock, so the actual SPI clock should be 1.25MHz. Maybe you should start from using the BSP default values and go from there. Best ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 8, 2025, 4:56pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/8 "2025-05-08T16:56:23Z")
Hello, Thank you for your instruction, here is my feed back. 1. SPI ID I’m using Vitis 2024.2, and DEVICE ID has been replaced with BASE ADDRESS in this version. 2. Initialization I checked [Adam Taylor SPI example](https://github.com/ATaylorCEngFIET/Part_217_SPI_Master_Salve/blob/master/project_1/project_1.sdk/spi_ps/src/helloworld.c) and I believe `XSpi_Initialize( &Spi, QSPI_DEVICE_ID );` is for Spi, not SpiPs. There is a differnece, generally speaking, SpiPs is driver for things running on PS, and Spi is for PL. I write my code follow xilinx `xspips_flash_polled_example.c` and `xspips_eeprom_polled_example.c`, you can find them on [embeddedsw/XilinxProcessorIPLib/drivers/spips/examples/xspips\_flash\_polled\_example.c at master · Xilinx/embeddedsw · GitHub](https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/spips/examples/xspips_flash_polled_example.c) and [embeddedsw/XilinxProcessorIPLib/drivers/spips/examples/xspips\_eeprom\_polled\_example.c at master · Xilinx/embeddedsw · GitHub](https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/spips/examples/xspips_eeprom_polled_example.c) . Take [SPI flash](https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/spips/examples/xspips_flash_polled_example.c) as an example, in Line 227, you can see that if SDT is defined (SDT is defined automaticlly in the latest version), there will be no need to use SPI ID, just BASE ADDRESS will do. And in both examples, I don’t find anything related to SPI initialization, no `XSpi_Initialize( &Spi, QSPI_DEVICE_ID );` exist. 3. LMK&LMX values I have tried defult values used by PYNQ downloaded from [here](https://github.com/Xilinx/RFSoC-PYNQ/blob/master/boards/RFSoC4x2/packages/tics/tics/register_txts/LMX2594_491.52.txt), it didn’t work, but I will try again later. 4. SPI clock 20 MHz for SPI clock is same with the PYNQ base layer. In LMK and LMX user manual, it said that SPI clock should not above 5MHz, that is why I use `XSpiPs_SetClkPrescaler(SpiInstancePtr, XSPIPS_CLK_PRESCALE_16)` to divied SPI clock to 1.25MHz, but I’m not sure is it working because there is no way put a scope on SPI bus. If you also have a RFSoC4x2 at hand, have you tried to use Vitis to program a bare-metal code to configure the LMK and LMX? If so, please share your finds with me, I’ll be much appreciated. Thank you for spending time reading my code! Best regards. ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 8, 2025, 6:07pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/9 "2025-05-08T18:07:52Z")
Hi, I haven’t used the newer versions yet. Thanks for explaining, it was educational for me. If the original file also didn’t work, your SPI is the problem. I check PYNQ repo again. Like you said, your clocks match there. However, I downloaded the board BSP from RealDigital website, that one uses 200 MHz clocks for SPI. So, I am not sure which one you should follow. Unfortunately, I haven’t used baremetal on RFSoC4x2. Let me know if anything changes. Best ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 9, 2025, 6:21am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/10 "2025-05-09T06:21:06Z")
I just tried default reg values, LMK 245.76MHz, LMX 491.52MHz, still not working. I believe somewhere of SPI settings went wrong, but after all the things I have tried, I can’t figure out the reason. I decided to use PYNQ, baremetal programming seems less populer, there is not much to reference. ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 9, 2025, 10:17am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/11 "2025-05-09T10:17:44Z")
New Progress! I mananged to write to LMK&LMX! It turns out that problem is not SPI, it is the programming requirement of the clock chips. LMK needs to set sel0, sel1 and rst signal, LMX needs to write register to rest first. After apply these code, 3 out of 4 LED turned on, they are ADC, DAC, PLL2. ![e26b75a857ed8a29936885b6c9d3371](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/8df57ed457224e8bb2bf99a01f77bbc70c158cff.jpeg) Now there is another strange problem, LMK04828B has two PLL, PLL1 use external clock as reference, and PLL2 use PLL1 as reference, but from the LED status, PLL2 was locked without the lock of PLL1. In this case, SPI writing is valid, both LMK and LMX was written, but PLL1 is not lock, why would this happen? I use ILA in Vivado to check the clk\_adc, which is set to 38.4MHz, and ILA clock is 749.999878MHz, here is the waveform. ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/a86162a796c4629acd879b15191513fa16bbb248.png) Latest code is attached, in case someone wants to try baremetal on RFSoC4x2, just one last step missing! [LMK\_LMX.c](https://discuss.pynq.io/uploads/short-url/jgnU0f3T9yvHF5c8IpbnP6R6zNl.c) (9.2 KB) [LMK\_LMX.h](https://discuss.pynq.io/uploads/short-url/n5SjVJrIBS9wZmjrjUHfLHkJhV.h) (847 Bytes) TICS pro files is also attached, is there anything wrong with it? [LMX2594\_491.52.txt](https://discuss.pynq.io/uploads/short-url/4R0iuUKqmGSb4HbxO1mtmE4ixAY.txt) (1.5 KB) [LMK04828\_245.76.txt](https://discuss.pynq.io/uploads/short-url/ce3icLbsBtaat5cYktsuc6v1KhH.txt) (2.0 KB) ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 9, 2025, 2:43pm UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/12 "2025-05-09T14:43:28Z")
Hi, This is great news indeed!😃 It seems you individually program LMX and LMK and used GPIOs for the signals you mentioned. I want to ask did you program FPGA to have those MIOs to be GPIO or not? > [@zuyuan\_xing](#): > > In this case, SPI writing is valid, both LMK and LMX was written, but PLL1 is not lock, why would this happen? Can you readback MUXout from SPI to confirm the lock? Like I mentioned before, I had a similar issue. The PLLs are locked, but not showing on LEDs. > [@zuyuan\_xing](#): > > I use ILA in Vivado to check the clk\_adc, which is set to 38.4MHz, and ILA clock is 749.999878MHz, here is the waveform. I never checked the output clocks from the RFDC. Is the clock period OK? For some regions, you have longer period. > [@zuyuan\_xing](#): > > TICS pro files is also attached, is there anything wrong with it? > [LMX2594\_491.52.txt](https://discuss.pynq.io/uploads/short-url/4R0iuUKqmGSb4HbxO1mtmE4ixAY.txt) (1.5 KB) > [LMK04828\_245.76.txt](https://discuss.pynq.io/uploads/short-url/ce3icLbsBtaat5cYktsuc6v1KhH.txt) (2.0 KB) Is this your configuration or the original one? Best ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 12, 2025, 6:12am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/13 "2025-05-12T06:12:06Z")
1. GPIOs Yes, I set them in Vivado, but it is in PS, not FPGA(PL). 2. Readback I can not read back from LMK, which is reasonable because it doesn’t have a SDO pin. And I also can’t read back from LMXs. 3. Output clocks Seems not corrcet from this figure, I’m expecting a 38.4MHz, but from the waveform, it is not even a stable clock, not to mention frequency. Maybe this error is caused by the unlocked PLL1 of LMK? ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/a86162a796c4629acd879b15191513fa16bbb248.png) 1. Tics file It is the original configuration, dowloaded from PYNQ github repository. ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 12, 2025, 7:26am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/14 "2025-05-12T07:26:58Z")
Summary for baremetal LMK&LMX program. 1. LMK should be initialize manually by GPIOs before writing registers. ```auto XGpioPs Gpio; XGpioPs_Config *GpioConfigPtr; GpioConfigPtr = XGpioPs_LookupConfig(XPAR_GPIO_BASEADDR); XGpioPs_CfgInitialize(&Gpio, GpioConfigPtr, GpioConfigPtr->BaseAddr); XGpioPs_SetDirectionPin(&Gpio, MIO_LMK_RST, 1); XGpioPs_SetOutputEnablePin(&Gpio, MIO_LMK_RST, 1); XGpioPs_WritePin(&Gpio, MIO_LMK_RST, 1);//lmk_reset.write(1) XGpioPs_WritePin(&Gpio, MIO_LMK_RST, 0);//lmk_reset.write(0) XGpioPs_SetDirectionPin(&Gpio, MIO_LMK_CLK_IN_SEL0, 1); XGpioPs_SetOutputEnablePin(&Gpio, MIO_LMK_CLK_IN_SEL0, 1); XGpioPs_WritePin(&Gpio, MIO_LMK_CLK_IN_SEL0, 0);//lmk_clk_sel0.write(0) XGpioPs_SetDirectionPin(&Gpio, MIO_LMK_CLK_IN_SEL1, 1); XGpioPs_SetOutputEnablePin(&Gpio, MIO_LMK_CLK_IN_SEL1, 1); XGpioPs_WritePin(&Gpio, MIO_LMK_CLK_IN_SEL1, 0);//lmk_clk_sel1.write(0) ``` 1. LMXs should be reset first, by writing reset values to register. ```auto u32 reset = 0x020000;//write reset TempBuffer[2] = reset & 0xFF; TempBuffer[1] = (reset>>8) & 0xFF; TempBuffer[0] = (reset>>16) & 0xFF; XSpiPs_SetSlaveSelect(SpiInstancePtr, slave_select); Status = XSpiPs_PolledTransfer(SpiInstancePtr, TempBuffer, NULL, 3); reset = 0x000000;//remove reset TempBuffer[2] = reset & 0xFF; TempBuffer[1] = (reset>>8) & 0xFF; TempBuffer[0] = (reset>>16) & 0xFF; Status = XSpiPs_PolledTransfer(SpiInstancePtr, TempBuffer, NULL, 3); ``` 1. Register values should be configured very carefully through TICS pro. I used PYNQ official register values, but it won’t work for PLL1 of LMK, it will not lock. Howerer, after I changed some settings for PLL1, it locked successfully. Download register values from [here](https://github.com/Xilinx/RFSoC-PYNQ/blob/master/boards/RFSoC4x2/packages/tics/tics/register_txts/LMK04828_245.76.txt), then load it in TICS, and change value of ‘Phase Dector Fre’, ‘PLL1 R Dividers’ and ‘N divider’ for PLL1 as shown in the figure. After that, export and use the HEX values. ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/4/49e9ea5d010ce216203a2a8c62fcb7a1fe50a565.png) If you want to build a baremetal project, code and register values for clk congifure is in the attached C code as a reference. [LMK\_LMX.c](https://discuss.pynq.io/uploads/short-url/i1lTRXiSgzT1gDdHCfKVdlJ1TeL.c) (11.0 KB) ---
**Author:** ![zuyuan\_xing](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/zuyuan_xing/32/6956_2.png) [@zuyuan\_xing](https://discuss.pynq.io/u/zuyuan_xing)\ **Post date:** [May 12, 2025, 7:28am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/15 "2025-05-12T07:28:34Z")
All solved, turns out the register values leads to the unlock of PLL1, please see my latest post. Thanks for your help! ---
**Author:** ![system](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/system/32/2_2.png) [@system](https://discuss.pynq.io/u/system)\ **Post date:** [May 15, 2025, 7:28am UTC](https://discuss.pynq.io/t/program-lmk-lmx-on-rfsoc4x2-from-vitis-no-pynq/8383/16 "2025-05-15T07:28:58Z")
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