# PYNQ OFDM demo issue

**URL:** <https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354>\
**Category:** Support\
**Created:** [March 15, 2023, 9:20pm UTC](https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354 "2023-03-15T21:20:02Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![pynqzen](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/pynqzen/32/97_2.png) [@pynqzen](https://discuss.pynq.io/u/pynqzen)\
**Post date:** [March 15, 2023, 9:20pm UTC](https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354/1 "2023-03-15T21:20:02Z")

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Hi,

I have wired the external breakpoint card per the instructions and installed the reference design from here using pip. The design can be found here:

> **[GitHub - strath-sdr/rfsoc\_ofdm: PYNQ example of an OFDM Transmitter and...](https://github.com/strath-sdr/rfsoc_ofdm)**
>
> PYNQ example of an OFDM Transmitter and Receiver on RFSoC. - GitHub - strath-sdr/rfsoc\_ofdm: PYNQ example of an OFDM Transmitter and Receiver on RFSoC.

This isn’t a custom design, nor have I changed anything in the notebooks. Should just work but does not.

“ofdm\_hw = Overlay()” never completes nor complains. When I stop the kernel it is in the middle of various codes, different places each time I stop it.

I am using a ZCU111 board and on the same board the QPSK demo from Strathclyde at least runs.

Has anyone ever seen this or have a remedy?

Kind regards,  
-Fred

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**Author:** ![pynqzen](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/pynqzen/32/97_2.png) [@pynqzen](https://discuss.pynq.io/u/pynqzen)\
**Post date:** [March 15, 2023, 9:43pm UTC](https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354/2 "2023-03-15T21:43:04Z")

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Hi, I did find this issue that seems related, however in my case I do have loopback connected. I will check the seating of my breakout board.

> <https://github.com/strath-sdr/rfsoc_ofdm/issues/6>
>
> The system will halt on initialisation if the system is not connected in loopbac…k. A kernel interrupt is required to fix the issue.

I’ll leave this open for a while and then close it if no one else has any insights.

Thank you,  
-Fred

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**Author:** ![Mostafa\_Shabani](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/mostafa_shabani/32/4787_2.png) [@Mostafa\_Shabani](https://discuss.pynq.io/u/Mostafa_Shabani)\
**Post date:** [June 19, 2023, 2:31am UTC](https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354/3 "2023-06-19T02:31:12Z")

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I have the same problem on a ZCU208 eval board. I don’t have the SSMP cables to connect the CLK-104 outputs to the DAC/ADC clock inputs; would that cause this problem? Is there an alternative way to set the clock sources to some clock on the eval board?

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [September 1, 2024, 10:40am UTC](https://discuss.pynq.io/t/pynq-ofdm-demo-issue/5354/4 "2024-09-01T10:40:11Z")

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Split this topic on September 1, 2024, 10:40am UTC

A post was split to a new topic: [The Strathclyde RFSoC Studio Installer for PYNQ RFSoC 4x2](https://discuss.pynq.io/t/the-strathclyde-rfsoc-studio-installer-for-pynq-rfsoc-4x2/7442)