# PYNQ RFSoC Board Queries

**URL:** <https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712>\
**Category:** Support\
**Created:** [September 28, 2022, 9:02pm UTC](https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712 "2022-09-28T21:02:19Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![KLN](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/kln/32/3779_2.png) [@KLN](https://discuss.pynq.io/u/KLN)\
**Post date:** [September 28, 2022, 9:02pm UTC](https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712/1 "2022-09-28T21:02:19Z")

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I’ve few questions on RFSoC 4x2 Kit ([https://www.rfsoc-pynq.io/](https://www.rfsoc-pynq.io/)) on QSFP28 100G connection from FPGA to connector.

It’s seen that GTY Tx lanes are swapped i.e as per the below attached excel.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/6/6c68d3bb00ac069ccef4dbf2b43f3f440a313b63.png)

Xilinx 100G Subsystem documents recommends lane swapping is allowable but the both TX and RX but in schematic it is contrary i.e., TX1 is connected to RX4 and TX4 is connected RX1 when in loopback cable which is voila ting the rule. Is this okay?

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**Author:** ![KLN](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/kln/32/3779_2.png) [@KLN](https://discuss.pynq.io/u/KLN)\
**Post date:** [September 28, 2022, 9:03pm UTC](https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712/2 "2022-09-28T21:03:05Z")

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Attached schematic section

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/1c0f3b40b2d389a2c1b587398967dc14a35f7e22.png)

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [September 29, 2022, 10:13am UTC](https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712/3 "2022-09-29T10:13:54Z")

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What problem are you seeing, and have you tried to test the QSFP interface?

> [@KLN](#):
>
> Is this okay?

It works the scenarios we’ve tested… board to board, board to NIC.

Cathal

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**Author:** ![andrea](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/andrea/32/1871_2.png) [@andrea](https://discuss.pynq.io/u/andrea)\
**Post date:** [May 4, 2023, 6:10am UTC](https://discuss.pynq.io/t/pynq-rfsoc-board-queries/4712/4 "2023-05-04T06:10:29Z")

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Hello Cathal,

we are experiencing an important problem with that.  
We instanciate a 10GbE core (PHY+MAC+UDP), by mapping only one lane.  
We use a QSFP to SFP breakout cable.  
We observe ARP packets transmitted from the board, but no data are received.

Any suggestion?

regards  
Andrea