# Question about the use case of overlay in PYNQ **URL:** \ **Category:** Support\ **Created:** [June 26, 2019, 7:52am UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252 "2019-06-26T07:52:10Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![NS\_Huang](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ns_huang/32/151_2.png) [@NS\_Huang](https://discuss.pynq.io/u/NS_Huang)\ **Post date:** [June 26, 2019, 7:52am UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252/1 "2019-06-26T07:52:10Z")
Hi, I have a basic question related to the use case of overlay in PYNQ. Provided that the application is implemented by SW in the PS and HW in the PL. The input data of the application is stored in the DRAM in advance. The SW is to control and configure the HW accelerator in the PL. However, the HW accelerator is divided by 3 sub-HW tasks in terms of serial execution in time i.e. sub HW A–\>sub HW B–\> sub HW C. All the communication among sub HW task A, B and C are through the DRAM which performance is enough. In the context, from the perspective of overlay in PYNQ, can use implement the HW by changing the contents of the PL on the fly like the following code ? Does the reloading new overlay not corrupt or ruin the status and SW code in the PS ? Are there any thing should be careful if loading overlay on the fly without impacting the PS ? Sample code in the .py to run on PYNQ #load the first HW overlap sub task to process in PL. output data is stored in the DRAM overlay = Overlay(‘/home/xilinx/sub\_HW\_1.bit’) … #load the second HW overlap sub task to process in PL. output data is stored in the DRAM overlay = Overlay(‘/home/xilinx/sub\_HW\_2.bit’) … #load the third HW overlap sub task to process in PL. output data is stored in the DRAM overlay = Overlay(‘/home/xilinx/sub\_HW\_3.bit’) .Thanks ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [June 26, 2019, 2:16pm UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252/2 "2019-06-26T14:16:28Z")
If I understand your question correctly, yes, you can reload the PL with different designs, and retain data in memory. You need to be careful you don’t reload a design while an AXI transaction is in progress. This can lock an AXI bus. (E.g. if you have a video stream running that is reading/writing to a framebuffer) You should make sure the PL design is “stopped” before loading the new design. Cathal ---
**Author:** ![madhura](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/madhura/32/270_2.png) [@madhura](https://discuss.pynq.io/u/madhura)\ **Post date:** [August 23, 2019, 7:22am UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252/3 "2019-08-23T07:22:37Z")
reload the PL with a different design is only through partial bit stream, is it? ---
**Author:** ![NS\_Huang](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ns_huang/32/151_2.png) [@NS\_Huang](https://discuss.pynq.io/u/NS_Huang)\ **Post date:** [August 23, 2019, 7:50am UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252/4 "2019-08-23T07:50:37Z")
Hi, The original question I asked was regarding the case of full bit stream for simplicity instead of partial bit stream. FYI Thanks All the best, Nan-Sheng ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 23, 2019, 8:14am UTC](https://discuss.pynq.io/t/question-about-the-use-case-of-overlay-in-pynq/252/5 "2019-08-23T08:14:01Z")
> [@NS\_Huang](#): > > l question I asked was regarding the case of full bit stream for simplicity instead of partial bit stream. No, you can (re)load a full bitstream at any time. Cathal