# Questions About PYNQ Framework **URL:** \ **Category:** Support\ **Created:** [March 30, 2024, 9:00am UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872 "2024-03-30T09:00:33Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![NNUT](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/nnut/32/3540_2.png) [@NNUT](https://discuss.pynq.io/u/NNUT)\ **Post date:** [March 30, 2024, 9:00am UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/1 "2024-03-30T09:00:34Z")
Hello! I’m unsure if I’m allowed to ask about the PYNQ framework here; if I’m not then I’ll ask on the Xilinx forums. I’ve found articles about how to load PL while linux is active (aka fpgautil) from here: _[AMD Technical Information Portal](https://docs.amd.com/r/en-US/ug1144-petalinux-tools-reference-guide/ZynqMP?tocId=JMgXKPkandHFFfdfPg3BYA)_ _[https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming?f=print#SolutionZynqMPPLProgramming-ExercisingFPGAprogrammingusingfpgautil](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming?f=print#SolutionZynqMPPLProgramming-ExercisingFPGAprogrammingusingfpgautil)_ Does PYNQ use the fpgautil to load hardware overlays into PL? How does PYNQ handle designs that include the ZYNQ in them? For example this example project: _[Tutorial: Creating a hardware design for PYNQ](https://discuss.pynq.io/t/tutorial-creating-a-hardware-design-for-pynq/145)_ I would think that you can’t reprogram the ZYNQ cores as they’re actively running linux. My goal is to learn more about how PYNQ operates as a whole. In my future projects, I want to be able to have my kria kv260 run Ubuntu, load a PL image, then allocate memory in kernel space for the PL. Thank you, Nick ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [April 2, 2024, 8:04am UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/2 "2024-04-02T08:04:57Z")
Hi @NNUT, PYNQ uses fpgamanager to download the bitstream. > > I would think that you can’t reprogram the ZYNQ cores as they’re actively running linux. There are certain registers that you can program at runtime, such as the PL clocks, AXI4 ports width, etc. I suggest you check the TRM for more information. Mario ---
**Author:** ![NNUT](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/nnut/32/3540_2.png) [@NNUT](https://discuss.pynq.io/u/NNUT)\ **Post date:** [April 10, 2024, 5:59am UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/3 "2024-04-10T05:59:00Z")
Hey Mario, I apologize for the late response. I was reading some of the pynq tutorial docs and found that when a bitstream is downloaded to the hardware manager → PL then the PS has corresponding IP drivers made available. Does PYNQ use the HWH file to look up IPs being used and consequently load their corresponding IP drivers (like AXI)? I did see some docs on fpgamanager but I got distracted with fpgautil. Also, I will take a look at the TRM. Thank you for the information, Nick ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [April 10, 2024, 2:43pm UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/4 "2024-04-10T14:43:14Z")
> [@NNUT](#): > > Does PYNQ use the HWH file to look up IPs being used and consequently load their corresponding IP drivers (like AXI)? Yes. You can see how to create your own driver here: [https://pynq.readthedocs.io/en/latest/overlay\_design\_methodology/overlay\_tutorial.html#Creating-a-Driver](https://pynq.readthedocs.io/en/latest/overlay_design_methodology/overlay_tutorial.html#Creating-a-Driver) Mario ---
**Author:** ![NNUT](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/nnut/32/3540_2.png) [@NNUT](https://discuss.pynq.io/u/NNUT)\ **Post date:** [April 15, 2024, 8:18pm UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/5 "2024-04-15T20:18:23Z")
Hey Mario, I think you’ve answered all of my questions. Thank you for your help! The last items of my concern involve driver config using Linux drivers directly instead of PYNQ and Python, but I think I need to ask those questions on the Vivado forum. Pynq will actually make it so I don’t need to worry about that complicated setup until the end of my project… so I can focus on the actual hardware design. Thank you for your help! ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [April 16, 2024, 2:04pm UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/6 "2024-04-16T14:04:01Z")
> [@NNUT](#): > > The last items of my concern involve driver config using Linux drivers directly instead of PYNQ and Python, but I think I need to ask those questions on the Vivado forum. Yes, those questions are more suited for the Xilinx forums. > Pynq will actually make it so I don’t need to worry about that complicated setup until the end of my project… so I can focus on the actual hardware design. That’s one of the PYNQ goals. ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [April 16, 2024, 2:04pm UTC](https://discuss.pynq.io/t/questions-about-pynq-framework/6872/7 "2024-04-16T14:04:07Z")